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上海交通大学:《模拟电子技术》课程教学资源(PPT课件)chapter 4 MOS Field-Effect Transistors(MOSFETs)

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4.0 Introduction 4.1 Device Structure and Physical Operation 4.2 Current-Voltage Characteristics 4.3 MOSFET Circuits at DC 4.4 The MOSFET as an Amplifier and as a Switch 4.5 Biasing in MOS Amplifier Circuits 4.6 Small-Signal Operation and Models 4.7 Single-Stage MOS Amplifiers 4.8 The MOSFET Internal Capacitances and High-Frequency Model 4.9 Frequency Response of the CS Amplifier 4.10 The CMOS Digital Logic Inverter 4.11 The Depletion-Type MOSFET 4.12 The SPICE MOSFET Model and Simulation Example
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Chapter 4MOSField-EffectTransistors(MOSFETS)2025/11/27

1 2025/11/27 MOS Field-Effect Transistors (MOSFETs) Chapter 4

2Content4.0Introduction4.1DeviceStructureandPhysicalOperation4.2Current-VoltageCharacteristics4.3MOSFETCircuitsat DC4.4TheMOSFETasanAmplifierandasaSwitch4.5BiasinginMOSAmplifierCircuits4.6Small-SignalOperationandModels4.7 Single-StageMOSAmplifiers4.8TheMOSFETInternalCapacitancesandHigh-FrequencyModel4.9FrequencyResponseoftheCSAmplifier4.10TheCMOSDigitalLogicInverter4.11 The Depletion-Type MOSFET4.12TheSPICEMOSFETModelandSimulationExample2025/11/27

Content 2025/11/27 2 4.0 Introduction 4.1 Device Structure and Physical Operation 4.2 Current-Voltage Characteristics 4.3 MOSFET Circuits at DC 4.4 The MOSFET as an Amplifier and as a Switch 4.5 Biasing in MOS Amplifier Circuits 4.6 Small-Signal Operation and Models 4.7 Single-Stage MOS Amplifiers 4.8 The MOSFET Internal Capacitances and High-Frequency Model 4.9 Frequency Response of the CS Amplifier 4.10 The CMOS Digital Logic Inverter 4.11 The Depletion-Type MOSFET 4.12 The SPICE MOSFET Model and Simulation Example

34.0Introduction to FETThree-terminaldevicesare far more useful thantwo-terminalones, because they can be used ina multitudeofapplications,signalamplificationdigital logicmemorycircuits.Thebasicprinciplethe use of the voltage betweentwo terminals to control the current flowing in the thirdterminal.>Transistor=transferresistorJ.P.Chen2025/11/27

4.0 Introduction to FET ⚫ Three-terminal devices are far more useful than two￾terminal ones, because they can be used in a multitude of applications, ➢ signal amplification ➢ digital logic ➢ memory circuits. ➢ . ⚫ The basic principle ⎯ the use of the voltage between two terminals to control the current flowing in the third terminal. ➢ Transistor = transfer resistor 2025/11/27 J.P. Chen 3

4.0Introduction to FETFET:FieldEffectTransistorTherearetwotypesMOSFET:metal-oxide-semiconductorFETJFET:JunctionFETMOSFETisalsocalled the insulated-gateFETorIGFET.>QuitesmallintelCore"i7> Simplemanufacturingprocess>Lowpowerconsumption>WidelyusedinVLSl circuits(>billionona singleIc chip)2025/11/27

2025/11/27 4 ⚫ FET: Field Effect Transistor ⚫ There are two types ➢ MOSFET: metal-oxide-semiconductor FET ➢ JFET: Junction FET ⚫ MOSFET is also called the insulated-gate FET or IGFET. ➢ Quite small ➢ Simple manufacturing process ➢ Low power consumption ➢ Widely used in VLSI circuits(>billion on a single IC chip) 4.0 Introduction to FET

54.1Device structure of MOSFET (n-type)Gate(G)Source(S)Drain(D)QoMetalOxideEHHZntnt(SiO2)Channelareap-type SemiconductorSubstrate(Body) Body(B)For normal operation, it is needed to create aconducting channel between Source and Drain2025/11/27

2025/11/27 5 4.1 Device structure of MOSFET (n-type) p-type Semiconductor Substrate (Body) Body(B) n + n + Oxide (SiO2 ) Source(S) Gate(G) Drain(D) Metal ⚫ For normal operation, it is needed to create a conducting channel between Source and Drain Channel area

64.1Creating a channel for current flow> An n channel can be induced atthe top of the substrate beneath+Gate electrodeUGSthe gate by applying a positiveInducedGSDOn-typevoltage to the gateOxide(SiO2)channel> The channel is an inversionlaver> The value of VGs at which ap-type substratesufficient number of mobileDepletionregionOBelectrons accumulate to form aconducting channel is called thethreshold voltage (V)2025/11/27

4.1 Creating a channel for current flow 2025/11/27 6 ➢An n channel can be induced at the top of the substrate beneath the gate by applying a positive voltage to the gate ➢The channel is an inversion layer ➢The value of VGS at which a sufficient number of mobile electrons accumulate to form a conducting channel is called the threshold voltage (Vt )

74.1Device structure of MOSFETMaindevicedimensionsfeature sizechannel lengthLSource (S)Gate (G)Drain (D)CO特征尺寸Oxide(SiO2)Metalchannel width(thickness=ta)> oxide thickness Tox (2ChannelnFregionto 50 nm)p-type substrateMetalG(Body)DOxide (SiO)SourceBodynegion(B)Cross-sectionviewp-type substrate(Body)ChannelregionBDrainregion2025/11/27

2025/11/27 7 ➢channel length L ➢channel width ➢oxide thickness Tox ( 2 to 50 nm) 4.1 Device structure of MOSFET Cross-section view feature size 特征尺寸 Main device dimensions

84.1ClassificationofFETAccordingtothetypeofthechannel,FETscanbeclassifiedasMOSFETEnhancementtypeNchannel·Depletiontype·EnhancementtypePchannel·DepletiontypeJFETPchannelNchannel2025/11/27

2025/11/27 8 ⚫ According to the type of the channel, FETs can be classified as ➢ MOSFET ▪ N channel ▪ P channel ➢ JFET ▪ P channel ▪ N channel 4.1 Classification of FET •Enhancement type •Depletion type •Enhancement type •Depletion type

94.1Drain current @ small voltage Vps> An NMOS transistor with Vcs > V, and with a small Vpsapplied.- The channel depth is uniform and the device acts as aresistance+UGSUps (small)> The channel conductance isGOTproportional to effective voltage,or excess gate voltage, (vgs_ V)> Drain current is proportional toInducedn-channel(VGs- V) and Vpsp-type substrateB二2025/11/27

4.1 Drain current @ small voltage vDS 2025/11/27 9 ➢An NMOS transistor with vGS > Vt and with a small vDS applied. − The channel depth is uniform and the device acts as a resistance. ➢The channel conductance is proportional to effective voltage, or excess gate voltage, (vGS – Vt ) . ➢Drain current is proportional to (vGS – Vt ) and vDS

104.1Drain currentsmall voltage 'psip (mA)VGS=V,+2V0.4UGS=V,+1.5V0.3UGS=V,+1 V0.2UGS=V,+0.5V0.1UGS≤V50Ups(m))01001502002025/11/27

4.1 Drain current @ small voltage vDS 2025/11/27 10

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