《现代计算机体系结构》课程教学课件（英文讲稿）Lecture 05 Core Pipelining

高级计算机体系结构设计及其在数据中心和云计算的应用Lecture 5Core Pipelining

高级计算机体系结构设计及其在数据中心和云计算的应 用 Lecture 5 Core Pipelining

高级计算机体系结构设计及其在数据中心和云计算的应用Before there was pipelining..Single-cycleinsno.(fetch,decodeexec)insn1.(fetch,decode,execMulti-cycleinsno.fetchinsno.decinsn0.execinsn1.fetchinsn1.decinsn1.exectimeSingle-cycle control:hardwired Low CPI (1)- Long clock period (to accommodate slowest instruction)Multi-cycle control:micro-programmed-Shortclockperiod- High CPICan we have both low CPl and short clock period?

高级计算机体系结构设计及其在数据中心和云计算的应 用 Before there was pipelining. • Single-cycle control: hardwired Single-cycle Multi-cycle insn0.(fetch,decode,exec) insn1.(fetch,decode,exec) insn0.fetch insn0.dec insn0.exec insn1.fetch insn1.dec insn1.exec time – Low CPI (1) – Long clock period (to accommodate slowest instruction) • Multi-cycle control: micro-programmed – Short clock period – High CPI • Can we have both low CPI and short clock period?

高级计算机体系结构设计及其在数据中心和云计算的应用PipeliningMulti-cycleinsno.fetchinsno.decinsn0.execinsn1.fetchinsn1.execinsn1.decinsno.fetchinsno.decinsno.execPipelinedinsn1.execinsn1.fetchinsn1.dectimeinsn2.fetchinsn2.decinsn2.execStart with multi-cycle designWhen insnO goes from stage 1 to stage 2... insn1 starts stage 1Each instruction passes through all stages.. but instructions enter and leave at faster rateCan have asmany insns in flight as there are stages

高级计算机体系结构设计及其在数据中心和云计算的应 用 Pipelining • Start with multi-cycle design Multi-cycle insn0.fetch insn0.dec insn0.exec insn1.fetch insn1.dec insn1.exec time Pipelined insn0.fetch insn0.dec insn0.exec insn1.fetch insn1.dec insn1.exec insn2.fetch insn2.dec insn2.exec • When insn0 goes from stage 1 to stage 2 . insn1 starts stage 1 • Each instruction passes through all stages . but instructions enter and leave at faster rate Can have as many insns in flight as there are stages

高级计算机体系结构设计及其在数据中心和云计算的应用PipelineExamples11addresshit?Stage delay = nBandwidth = ~(1/n)Dhit?addressStage delay =n/2Bandwidth = ~(2/naddresshit?Stage delay = n/3一Bandwidth = ~(3/n)Increasesthroughput at the expense of latency

高级计算机体系结构设计及其在数据中心和云计算的应 用 Pipeline Examples address hit? = = = = address = hit? = Increases throughput at the expense of latency = = = address hit? = = = =

高级计算机体系结构设计及其在数据中心和云计算的应用Processor PipelineReviewDecodeFetchExecuteMemory(Write-back)RegALUI-cacheD-cacheFile

高级计算机体系结构设计及其在数据中心和云计算的应 用 Processor Pipeline Review +4 Fetch Decode Memory (Write-back) Execute I-cache Reg File PC +4 ALU D-cache

高级计算机体系结构设计及其在数据中心和云计算的应用Stage 1: Fetch. Fetch an instruction from memory every cycle- UsePCtoindexmemory-IncrementPC(assumenobranchesfornow)Write state to the pipeline register (IF/ID)- The next stage will read this pipeline register

高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 1: Fetch • Fetch an instruction from memory every cycle – Use PC to index memory – Increment PC (assume no branches for now) • Write state to the pipeline register (IF/ID) – The next stage will read this pipeline register

高级计算机体系结构设计及其在数据中心和云计算的应用Stage 1: Fetch Diagramtarget.MU十I+OdaPCosInstructionSCacheerIF / IDPipelineregister

高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 1: Fetch Diagram 1 + M U X PC + 1 Decode target Instruction bits IF / ID Pipeline register PC Instruction Cache en en Decode

高级计算机体系结构设计及其在数据中心和云计算的应用Stage 2: DecodeDecodesopcodebits- Set up Control signals forlater stagesReadinputoperandsfromregisterfile-Specified bydecodedinstructionbitsWrite state to the pipeline register (ID/EX)-Opcode- Register contents- PC+1 (even though decode didn't use it)- Control signals (from insn) for opcode and destReg

高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 2: Decode • Decodes opcode bits – Set up Control signals for later stages • Read input operands from register file – Specified by decoded instruction bits • Write state to the pipeline register (ID/EX) – Opcode – Register contents – PC+1 (even though decode didn’t use it) – Control signals (from insn) for opcode and destReg

高级计算机体系结构设计及其在数据中心和云计算的应用Stage 2: Decode DiagramtargetI+I+OdregAearegBeeiRegisterFiledestRegdataSaeesIF / IDID/EXPipelineregisterPipelineregister

高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 2: Decode Diagram regA contents Register File regA regB PC + 1 PC + 1 Fetch Execute destReg target ID / EX Pipeline register regB contents Register File en Instruction bits IF / ID Pipeline register Control signals Fetch Execute destReg data

高级计算机体系结构设计及其在数据中心和云计算的应用Stage 3: Execute.PerformALUoperations- Calculate result of instruction·Control signals select operation·Contentsof regAusedas oneinput: Either regB or constant offset (from insn) used as second input-CalculatePC-relativebranchtargetPC+1+(constantoffset) Write state to the pipeline register (EX/Mem)- ALU result, contents of regB, and PC+1+offset- Control signals (from insn) for opcode and destReg

高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 3: Execute • Perform ALU operations – Calculate result of instruction • Control signals select operation • Contents of regA used as one input • Either regB or constant offset (from insn) used as second input – Calculate PC-relative branch target • PC+1+(constant offset) • Write state to the pipeline register (EX/Mem) – ALU result, contents of regB, and PC+1+offset – Control signals (from insn) for opcode and destReg