《现代计算机体系结构》课程教学课件（留学生版）Lecture 6 Memory Hierarchy and Cache

ComputerArchitectureMemory Hierarchy and CacheComputerArchitecture

Computer Architecture Computer Architecture Memory Hierarchy and Cache

Why Are You Here for This Course?"C" as a model of computationC ProgrammingProgrammer'sviewofacomputersystemworksHowdoesanassemblyArchitect/microarchitect'sview.program end up executing asHowtodesignacomputerthatdigital logic?meetssystemdesignqoalsChoicescriticallyaffectbothWhat happens in-between?theSWprogrammerandtheHWdesignerHowisacomputerdesignedusing logic gates and wires tosatisfy specific goals?HWdesigner'sview ofacomputersystemworksLogic DesignDigital logic as amodelofcomputationComputerArchitecture

Computer Architecture • How does an assembly program end up execu4ng as digital logic? • What happens in-between? • How is a computer designed using logic gates and wires to sa4sfy specific goals? C Programming Logic Design “C” as a model of computation Digital logic as a model of computation Programmer’s view of a computer system works HW designer’s view of a computer system works Architect/microarchitect’s view: How to design a computer that meets system design goals. Choices critically affect both the SW programmer and the HW designer Why Are You Here for This Course?

IdealismPipelineInstructionData(InstructionSupplySupplyexecution)- No pipeline stalls-Zero-cycle latency-Zero-cyclelatency-Perfectdataflow-Infinite capacity- Infinite capacity(reg/memory dependencies)- Zero cost-Infinitebandwidth-Zero-cycle interconnect(operand communication)-Perfectcontrolflow- Zero cost-Enoughfunctional units-Zero latency computeComputerArchitecture

Computer Architecture Idealism 3 Instruction Supply Pipeline (Instruction execution) Data Supply - Zero-cycle latency - Infinite capacity - Zero cost - Perfect control flow - No pipeline stalls -Perfect data flow (reg/memory dependencies) - Zero-cycle interconnect (operand communication) - Enough functional units - Zero latency compute - Zero-cycle latency - Infinite capacity - Infinite bandwidth - Zero cost

The Memory HierarchyComputerArchitecture

Computer Architecture The Memory Hierarchy

Memorv in a Modern SvstemL2CACHE1L2CACHESHAREDL3CACHE品COREOCORE1DRAMBANKS0DRAMMEMORYLCACHEACECACHECORE2CORE3咖NComputerArchitecture

Computer Architecture Memory in a Modern System 5 EQTG"3" N4"ECEJG"2" UJCTGF"N5"ECEJG" FTCO"KPVGTHCEG" EQTG"2" EQTG"4" EQTG"5" N4"ECEJG"3" N4"ECEJG"4" N4"ECEJG"5" FTCO"DCPMU" DRAM MEMORY CONTROLLER

Ideal Memory: Zero access time (latency).Infinite capacity?Zero cost: Infinite bandwidth (to support multiple accesses inparallel)ComputerArchitecture

Computer Architecture Ideal Memory • Zero access time (latency) • Infinite capacity • Zero cost • Infinite bandwidth (to support multiple accesses in parallel) 6

The Problem: Ideal memory's requirements oppose each other·Bigger is slower- Bigger →> Takes longer to determine the location.Faster is more expensive- Memory technology: SRAM vs. DRAM.Higher bandwidth is more expensiveNeed more banks, more ports, higher frequency, orfaster technologyComputerArchitecture

Computer Architecture The Problem • Ideal memory’s requirements oppose each other • Bigger is slower – Bigger à Takes longer to determine the location • Faster is more expensive – Memory technology: SRAM vs. DRAM • Higher bandwidth is more expensive – Need more banks, more ports, higher frequency, or faster technology 7

Memory Technology: DRAM: Dynamic random access memory: Capacitor charge state indicates stored value- Whether the capacitor is charged or discharged indicatesstorage of 1 or 0- 1 capacitor- 1 access transistorrowenable Capacitor leaks through the RC pathue- DRAM cell loses charge over time- DRAM cell needs to be refreshedComputerArchitecture

Computer Architecture Memory Technology: DRAM • Dynamic random access memory • Capacitor charge state indicates stored value – Whether the capacitor is charged or discharged indicates storage of 1 or 0 – 1 capacitor – 1 access transistor • Capacitor leaks through the RC path – DRAM cell loses charge over time – DRAM cell needs to be refreshed 8 row enable _ bitline

Memory Technology: SRAM: Static random access memory. Two cross coupled inverters store a single bit- Feedback path enables the stored value to persist in the"cell"- 4transistors for storage- 2 transistors for accessrowselectuennComputerArchitecture

Computer Architecture • Static random access memory • Two cross coupled inverters store a single bit – Feedback path enables the stored value to persist in the “cell” – 4 transistors for storage – 2 transistors for access Memory Technology: SRAM 9 row select bitline _ bitline

Memory Bank Organization and OperationReadaccesssequence:2DStorage1.Decoderowaddress&driveword-linesArrayerMSbits2.Selectedbitsdrivebit-lines.Entire row read3.Amplify row data4. Decode columnLSbitsColumnDecoderaddress&selectsubsetof row.Send to outputData Out5.Prechargebit-lines·FornextaccessComputerArchitecture10

Computer Architecture Memory Bank Organization and Operation • Read access sequence: 1. Decode row address & drive word-lines 2. Selected bits drive bit-lines • Entire row read 3. Amplify row data 4. Decode column address & select subset of row • Send to output 5. Precharge bit-lines • For next access 10