《现代计算机体系结构》课程教学课件（留学生版）Lecture 0 Introduction and Performance Evaluation

ComputerArchitectureIntroduction &Quantitative Design and AnalysisComputerArchitecture

Computer Architecture Computer Architecture Introduc1on & Quan1ta1ve Design and Analysis

Why Are You Here for This Course?"c"as a model of computationC ProgrammingProgrammer'sviewofacomputersystemworksHowdoesanassemblyArchitect/microarchitect'sview:program end up executing asHowtodesign acomputerthatdigital logic?meetssystemdesigngoalsWhat happens in-between?ChoicescriticallyaffectboththeSWprogrammerandHowisacomputerdesignedthe HW designerusing logic gates and wires tosatisfy specific goals?HW designer's view of acomputersystemworksLogic DesignDigital logic as amodelofcomputationComputerArchitecture

Computer Architecture • How does an assembly program end up execu4ng as digital logic? • What happens in-between? • How is a computer designed using logic gates and wires to sa4sfy specific goals? C Programming Logic Design “C” as a model of computa4on Digital logic as a model of computa4on Programmer’s view of a computer system works HW designer’s view of a computer system works Architect/microarchitect’s view: How to design a computer that meets system design goals. Choices cri<cally affect both the SW programmer and the HW designer Why Are You Here for This Course? 2

Levels of Transformation“Thepurposeof computingis insight"(Richard Hamming)WegainandgenerateinsightbysolvingproblemsHowdoweensureproblemsaresolvedbyelectrons?ProblemAlgorithmProgram/LanguageRuntimeSystemISA (Architecture)MicroarchitecturealCircuitsElectronsComputerArchitecture

Computer Architecture Microarchitecture ISA (Architecture) Program/Language Algorithm Problem Logic Circuits Runtime System (VM, OS, MM) Electrons “The purpose of compu4ng is insight” (Richard Hamming) We gain and generate insight by solving problems How do we ensure problems are solved by electrons? Levels of Transforma4on 3

ThePowerofAbstraction. Levels of transformation create abstractionsAbstraction:Ahigherlevelonlyneedstoknowabouttheinterfacetothelowerlevel,nothowthelowerlevelisimplemented- E.g., high-level language programmer does not really need toknow what the IsA is and how a computer executes instructions. Abstraction improves productivity- No need to worry about decisions made in underlying levelsE.g.,programming in Javavs.Cvs.assembly vs.binaryvs.byspecifying control signals of each transistor every cycle. Then, why would you want to know what goes onunderneath or above?ComputerArchitecture

Computer Architecture • Levels of transformation create abstractions – Abstraction: A higher level only needs to know about the interface to the lower level, not how the lower level is implemented – E.g., high-level language programmer does not really need to know what the ISA is and how a computer executes instructions • Abstraction improves productivity – No need to worry about decisions made in underlying levels – E.g., programming in Java vs. C vs. assembly vs. binary vs. by specifying control signals of each transistor every cycle • Then, why would you want to know what goes on underneath or above? The Power of Abstrac4on 4

Crossing the Abstraction Layers: As long as everything goes well, not knowing what happensin the underlying level (or above) is not a problem..WhatifTheprogramyouwroteisrunningslow?Theprogram youwrotedoes not run correctly?Theprogramyouwroteconsumestoomuchenergy?.What if-Thehardwareyoudesigned istoohardtoprogram?Thehardwareyoudesignedistooslowbecauseitdoesnotprovidetherightprimitivestothe software?One goal of this course is to understand how a processorworksunderneaththesoftwarelayerandhowdecisionsmade in hardware affect the software/programmerComputerArchitecture

Computer Architecture • As long as everything goes well, not knowing what happens in the underlying level (or above) is not a problem. • What if – The program you wrote is running slow? – The program you wrote does not run correctly? – The program you wrote consumes too much energy? • What if – The hardware you designed is too hard to program? – The hardware you designed is too slow because it does not provide the right primitives to the software? • One goal of this course is to understand how a processor works underneath the software layer and how decisions made in hardware affect the software/programmer Crossing the Abstrac4on Layers 5

AnExample:Multi-CoreSystemsMulti-CoreChipL2CACHEL2CACHESHAREDL3CACHECOREOCORE1DRAM BANKSWne-DRAM MEMORYCONTROLLERRFACE人NCACHECACHECORE3CORE2-乙*Diephotocredit:AMDBarcelonaComputerArchitecture

Computer Architecture EQTG"3" N4"ECEJG"2" UJCTGF"N5"ECEJG" FTCO"KPVGTHCEG" EQTG"2" EQTG"4" EQTG"5" N4"ECEJG"3" N4"ECEJG"4" N4"ECEJG"5" FTCO"DCPMU" Multi-Core Chip *Die photo credit: AMD Barcelona DRAM MEMORY CONTROLLER An Example: Mul4-Core Systems 6

UnexpectedSlowdownsinMulti-CoreHigh priority43.53.043MemoryPerformanceHog2.5Low priorityumopmos21.51.0710.50matlabgcc(Core 0)(Core 1)ComputerArchitecture

Computer Architecture 1.07% 3.04% 0% 0.5% 1% 1.5% 2% 2.5% 3% 3.5% 4% matlab% gcc% Slowdown% Ogmqt{"Rgthqtmcpeg"Jqi" Nqy"rtkqtkv{" Jkij"rtkqtkv{" (Core 0) (Core 1) Unexpected Slowdowns in Mul4-Core 7

AnQuestionorTwo Can you figure out why there is a disparity inslowdowns if you do not know how the processorexecutes the programs? Can you fix the problem without knowing what ishappening"underneath"?ComputerArchitecture

Computer Architecture • Can you figure out why there is a disparity in slowdowns if you do not know how the processor executes the programs? • Can you fix the problem without knowing what is happening “underneath”? An Ques4on or Two 8

Why the Disparity in Slowdowns?Multi-CoregccChipL2L2CACHECACHEunfairness↑HINTERCONNECTSharedDRAMMemorySystemDRAMMEMORYCONTROLLERDRAMDRAMDRAMDRAMBank 3BankoBank 1Bank 2ComputerArchitecture

Computer Architecture Why the Disparity in Slowdowns? CORE 1 CORE 2 L2 CACHE L2 CACHE DRAM MEMORY CONTROLLER DRAM Bank 0 DRAM Bank 1 DRAM Bank 2 Shared DRAM Memory System Multi-Core Chip unfairness INTERCONNECT matlab gcc DRAM Bank 3 9

DRAMBankOperationAccessAddressColumns(Row0,Column0)(Row0,Column1)(Row0.Column85)(Row1,Column0)RowSRowaddress0Row1RowBuffereONFLicT!Column muxColumnaddress@5DataComputerArchitecture10

Computer Architecture DRAM Bank Opera4on Row Buffer (Row 0, Column 0) Row decoder Column mux Row address 0 Column address 0 Data Row 0 Empty (Row 0, Column 1) Column address 1 (Row 0, Column 85) Column address 85 (Row 1, Column 0) HIT Row address 1 Row 1 Column address 0 CONFLICT ! Columns Rows Access Address: 10