《现代计算机体系结构》课程教学课件（英文讲稿）Lecture 07 Instruction Decode

高级计算机体系结构设计及其在数据中心和云计算的应用Lecture 7Instruction Decode

高级计算机体系结构设计及其在数据中心和云计算的应用 Lecture 7 Instruction Decode

高级计算机体系结构设计及其在数据中心和云计算的应用RiSC ISA Format. This should be review...Fixed-length.MIPSallinstsare32-bits/4bytes一Fewformats: MiPs has 3 formats: R (reg, reg, reg), I (reg, reg, imm), J (addr)·Alphahas5:Operate,Opw/Imm,Mem,Branch,Fp- Regularity across formats (when possible/practical)MiPs&Alphaopcodeinsamebit-positionforallformats.MiPS rs& rt fields in samebit-positionforRandIformats.Alphara/fafieldinsamebit-positionforall5formats

高级计算机体系结构设计及其在数据中心和云计算的应用 RISC ISA Format • This should be review. – Fixed-length • MIPS all insts are 32-bits/4 bytes – Few formats • MIPS has 3 formats: R (reg, reg, reg), I (reg, reg, imm), J (addr) • Alpha has 5: Operate, Op w/ Imm, Mem, Branch, FP – Regularity across formats (when possible/practical) • MIPS & Alpha opcode in same bit-position for all formats • MIPS rs & rt fields in same bit-position for R and I formats • Alpha ra/fa field in same bit-position for all 5 formats

高级计算机体系结构设计及其在数据中心和云计算的应用RISC Decode (MIPS)2156lopcodeotherfuncR-formatonlyopcode[2,0]000xxx=Br/Jump(exceptfor0ooooo)010o11100101110000jalbeqfuncbneblezrtbgtz0oDaddisltiandiluiaddiusltiuorixori[e's]010rso0lxxx=Immediateo1Cio=xxxx(1S:IXIa7:0X1)00IbIhIwlIwIbuIhuIwro1sbshswlSWswr10lwc3IwcoIwclIwc21SWc3SwcOswcISWC2

高级计算机体系结构设计及其在数据中心和云计算的应用 RISC Decode (MIPS) opcode 6 other 21 func 5 R-format only opcode[2,0] 000 001 010 011 100 101 110 111 000 func rt j jal beq bne blez bgtz 001 addi addiu slti sltiu andi ori xori lui 000xxx = Br/Jump (except for 000000) opcode[5,3] 001 addi addiu slti sltiu andi ori xori lui 010 rs rs rs rs 011 100 lb lh lwl lw lbu lhu lwr 101 sb sh swl sw swr 110 lwc0 lwc1 lwc2 lwc3 111 swc0 swc1 swc2 swc3 1xxxxx = Memory (1x0: L D, 1x1: ST) 001xxx = Immediate

高级计算机体系结构设计及其在数据中心和云计算的应用PLA Decoders (1/2)PLA=Programmable Logic ArraySimple logic to transform opcode to control signals isjump =!op5&!op4 &!op3 & (op2/op1/op0)-use_funct=!op5&!op4&!op3&!op2&!op1&!op0use_imm=op51!op5&!op4&op3is_load=op5&!op3-is_store=op5&op3

高级计算机体系结构设计及其在数据中心和云计算的应用 PLA Decoders (1/2) • PLA = Programmable Logic Array • Simple logic to transform opcode to control signals – is_jump = !op5 & !op4 & !op3 & (op2 | op1 | op0) – use_funct = !op5 & !op4 & !op3 & !op2 & !op1 & !op0 – use_imm = op5 | !op5 & !op4 & op3 – is_load = op5 & !op3 – is_store = op5 & op3

高级计算机体系结构设计及其在数据中心和云计算的应用PLA Decoders (2/2)OP5OP44-inputAND gateOP3ANDArrayOP2OPIOPois_storeis_loadORis_memuse_immArray2-input OR gateuse functis_jump

高级计算机体系结构设计及其在数据中心和云计算的应用 PLA Decoders (2/2) op5 op4 op3 op2 op1 AND Array 4-input AND gate op1 op0 is_store is_load use_imm use_funct is_jump OR is_mem Array 2-input OR gate

高级计算机体系结构设计及其在数据中心和云计算的应用Superscalar Decode for RiSC ISAsDecode Xinsns.per cycle (e.g,4-wide)-Justduplicatethehardware-Instructionsalignedat32-bitboundariesI-Fetch4-wide superscalarfetch32-bitinst32-bitinst32-bitinst32-bitinst32-bit instDecoderDecoderDecoderDecoderDecoderdecodeddecodeddecodeddecodeddecodedinstinstinstinstinstscalarsuperscalar

高级计算机体系结构设计及其在数据中心和云计算的应用 Superscalar Decode for RISC ISAs • Decode X insns. per cycle (e.g., 4-wide) – Just duplicate the hardware – Instructions aligned at 32-bit boundaries 1-Fetch 4-wide superscalar fetch 32-bit inst Decoder decoded inst scalar Decoder Decoder Decoder 32-bit inst Decoder decoded inst superscalar 4-wide superscalar fetch 32-bit inst 32-bit inst 32-bit inst decoded inst decoded inst decoded inst 1-Fetch

高级计算机体系结构设计及其在数据中心和云计算的应用CISC ISARisCfocus onfastaccess to information- Easy decode, IS, large RF's, Ds· Cisc focus on max expressiveness per min space-Designedinerawithfewertransistors,chips- Each memory access very expensive.Packasmuchworkintoasfewbytesaspossible.More“expressive"instructions-Better potential code generation in theory- More complex code generation in practice

高级计算机体系结构设计及其在数据中心和云计算的应用 CISC ISA • RISC focus on fast access to information – Easy decode, I$, large RF’s, D$ • CISC focus on max expressiveness per min space – Designed in era with fewer transistors, chips – Each memory access very expensive • Pack as much work into as few bytes as possible • More “expressive” instructions – Better potential code generation in theory – More complex code generation in practice

高级计算机体系结构设计及其在数据中心和云计算的应用ADDinRISCISAModeExampleMeaningRegisterADD R4,R3, R2R4=R3+R2

高级计算机体系结构设计及其在数据中心和云计算的应用 Mode Example Meaning Register ADD R4, R3, R2 R4 = R3 + R2 ADD in RISC ISA

高级计算机体系结构设计及其在数据中心和云计算的应用ADD in CISCISAModeExampleMeaningRegisterADD R4,R3R4 = R4 + R3ImmediateADD R4,#3R4 = R4 + 3DisplacementADD R4, 100(RI)R4 = R4 + Mem[100+RI]Register IndirectADD R4, (RI)R4 = R4 + Mem[RI]Indexed/BaseADD R3,(RI+R2)R3 = R3 + Mem[RI+R2]Direct/AbsoluteADD RI,(1234)RI = RI + Mem[1234]Memory IndirectADD RI, @(R3)RI = RI + Mem[Mem[R3]]Auto-lncrementADD RI,(R2)+RI = RI + Mem[R2]; R2++Auto-DecrementADD RI, -(R2)R2--; RI = RI + Mem[R2]

高级计算机体系结构设计及其在数据中心和云计算的应用 Mode Example Meaning Register ADD R4, R3 R4 = R4 + R3 Immediate ADD R4, #3 R4 = R4 + 3 Displacement ADD R4, 100(R1) R4 = R4 + Mem[100+R1] Register Indirect ADD R4, (R1) R4 = R4 + Mem[R1] ADD in CISC ISA Indexed/Base ADD R3, (R1+R2) R3 = R3 + Mem[R1+R2] Direct/Absolute ADD R1, (1234) R1 = R1 + Mem[1234] Memory Indirect ADD R1, @(R3) R1 = R1 + Mem[Mem[R3]] Auto-Increment ADD R1,(R2)+ R1 = R1 + Mem[R2]; R2++ Auto-Decrement ADD R1, -(R2) R2-; R1 = R1 + Mem[R2]

高级计算机体系结构设计及其在数据中心和云计算的应用x86CISC, stemmingfrom the original 4004 (~1971)Example:“"Move"instructions-GeneralPurposedatamovement: R>R,M>R, R>M,I>R,>MExchanges.EAX<>ECX,byteorderwithinaregister-StackManipulation.pushpopR<>Stack,PUSHA/POPA-TypeConversion-ConditionalMovesManywaysto dothesame/similaroperation

高级计算机体系结构设计及其在数据中心和云计算的应用 x86 • CISC, stemming from the original 4004 (~1971) • Example: “Move” instructions – General Purpose data movement • RR, MR, RM, IR, IM – Exchanges • EAX ↔ ECX, byte order within a register – Stack Manipulation • push pop R ↔ Stack, PUSHA/POPA – Type Conversion – Conditional Moves Many ways to do the same/similar operation