电子科技大学：《集成电路可测性设计 VLSIDesign》课程教学资源（课件讲稿）第10章 电流测试

●●●● ●●o ● ● 第十章电流测试 2

2 第十章 电流测试

●●● 8888o ●●●● ●●●● 本章要点 ●●●● ●●o● ●lbDa的定义 ●lbDa测试原理 ●lbDa可检测的故障 3

3 本章要点  IDDQ的定义  IDDQ测试原理  IDDQ可检测的故障

●● ●0 ● ●● 概述 ●●●● ●●●● Early 1990%s-Fabrication Line had 50 to 1000 defects per million (dpm)chips IBM wants to get 3.4 defects per million(dpm)chips (0 defects) Conventional way to reduce defects: Increasing test fault coverage Increasing burn-in coverage Increase Electro-Static Damage awareness New way to reduce defects: >IDo Testing-also useful for Failure Effect Analysis 4

4 概述  Early 1990’s – Fabrication Line had 50 to 1000 defects per million (dpm) chips  IBM wants to get 3.4 defects per million (dpm) chips (0 defects)  Conventional way to reduce defects:  Increasing test fault coverage  Increasing burn-in coverage  Increase Electro-Static Damage awareness  New way to reduce defects:  IDDQ Testing – also useful for Failure Effect Analysis

●●● ●● ●●0 ●● 1oa测试图形提高故障覆盖率 ●●● ●●0● ●●● ● 20% 5 100K-1M Iddg test (vectors) Functional and stuck-at test (vectors) 5

5 IDDQ测试图形提高故障覆盖率

●● bpa测试 ●●● 00 ●●0 ●●0● lDD---Current flow through VDD Q---Quiescent state IDDo Testing --Detecting faults by monitoring IDDQ 仝DD IDD Inputs CMOS Outputs circuit

IDDQ测试 IDD --- Current flow through VDD Q --- Quiescent state IDDQ Testing --- Detecting faults by monitoring IDDQ CMOS circuit Inputs Outputs VDD IDD

●● ● ●● 电压测量Vs电流测量 ●●●● ●●●● 。电压测量 VIH:VIL 。VoH,VoL ●电流测量 o IH,h DDQ Figure 4-TS-900 PXI Semiconductor Test System with pogo pin receiver self-test fixture http://www.eepw.com.cn/article/201708/363140.htm

7 电压测量vs电流测量  电压测量  VIH,VIL  VOH,VOL  电流测量  IIH,IIL  IDD  IDDQ http://www.eepw.com.cn/article/201708/363140.htm

●●4 lba测试--实际应用 ● ●● ●●●● ●●0● -STAR QD-1011 TEST VouT The Current Test Company Product Highlights QD-1011 Advanced(Delta)IDDQ Measurement Instrument Supporting Various Test Applications FEATURES APPLICATIONS .Wide DUT Supply range:VouT 0.5V to 7V CBU DoUT .Wide measurement range:IDDQ =0-30mA .ATE Probe Card Applications CMU ·Typical measurement time:1c0μs ATE Interface Board Applications Current PU .Delta IDDo Measurements Bypass Unit Current Measuring Unit High capacitive driving capability.up to 10uF .High single sample resolution:20nARMs Pre Post Stress Delta IDDQ Processing Unit 16-bits Iopa Value Read Out IDDO Pass/Fail Measurements .3-Wire Serial Configuration/Read out Interface .IDDo Read Out Measurements .On-board data processing capabilities Ippo Window Comparisons DESCRIPTION The QD-1011 is a full featured,advanced configurable quiescent supply current (IDDQ)measurement instrument, supporting both probe and final test and designed for probe DUT Control card and interface board applications.The instrument supports a wide range of IpDo test and measurements applications and provides digital measurement values as well as a pass/fail output signal.On-board memory and data processing capabilities allow implementing a wide range of basic and ATE advanced current based test strategies. test vectors The QD-1011 operates according to the Stabilised Voltage Drop principle and is designed to be inserted between the Automated Test Equipment (ATE)device power supply and the supply pin(s)of the Device Under Test(DUT).There is no need to remove the local on-pin decoupling capacitors.Its unique design ensures transparency to both the ATE and DUT,under all QD-1011 Application 2015年资料 8

8 IDDQ测试---实际应用 2015年资料

●●● ●●●0 ●●●● ●●o● 10.1lba测试机理 9

9 10.1 IDDQ测试机理

●● 10.1.1基本概念 ●●●● ●● 。定义 ·lbpa 静态电源电流(Quiescent state) ● lb0a测试--. 根据CMOS电路静态时电源电流非 常小的原理（几乎为0)，而大多数故障引起升高的 电源电流，因此可根据DDQ测试的电流大小判断被 测电路(CUT)是否存在故障 10

10 10.1.1 基本概念  定义  IDDQ -------- 静态电源电流(Quiescent state)  IDDQ测试-------- 根据CMOS电路静态时电源电流非 常小的原理（几乎为0）, 而大多数故障引起升高的 电源电流, 因此可根据IDDQ测试的电流大小判断被 测电路（CUT）是否存在故障

● ●●0 常通故障(Stuck-On)例子 ●●● ●●●● As-a-0的测试矢量 pMOS 故障电路 Ippo路径 Stuck- short 好电路状态 0 (X) nMOS 有故障电路状态 2021/8/18 集成电路可测性设计 11

2021/8/18 集成电路可测性设计 11 常通故障（ Stuck-On ）例子 A B VDD C pMOS nMOS Stuck￾short 1 0 0 (X) 好电路状态 有故障电路状态 A s-a-0的测试矢量 故障电路 IDDQ 路径