上海交通大学：《数字集成电路 Digital Integrated Circuit》课程教学资源（课程实验）HSPICE SIMULATION

DIC 2014 lab1 TA:Pengzhi Chu MicroE@SJTU HSPICE SIMULATION

HSPICE SIMULATION DIC_2014_lab1 TA: Pengzhi Chu MicroE@SJTU

Outline Introduction to Hspice Hspice simulation lab1 Lab Report

Outline  Introduction to Hspice  Hspice simulation_lab1  Lab Report

Hspice Introduction SPICE-Simulation Program with Integrated Circuit Emphasis developed by U.C.Berkeley SPICE simulate your electrical circuit designs,based on circuit level. Steady-state (DC Analysis) Time (Transient Analysis) Frequency (AC Analysis) ■

Hspice Introduction  SPICE – Simulation Program with Integrated Circuit Emphasis developed by U.C.Berkeley  SPICE simulate your electrical circuit designs, based on circuit level. Steady-state (DC Analysis) Time (Transient Analysis) Frequency (AC Analysis)

Hspice Introduction HSPICE Models Analog/RF Custom digital Standard cell Signal integrity

Hspice Introduction

Basic Netlist Structure Title ■Device models or ■.SUBCKT ■.OPTIONS ■Netlist (conditions for ■.ENDS simulation) ☐Output format ☐Analysis&temp. ■.ALTER ☐.lc(initial state) ■Netlist ■.GLOBAL ■.END ■.PARAM ■Source ■Netlist

Basic Netlist Structure Title * or $ .OPTIONS (conditions for simulation) Analysis & temp. .IC (initial state) .GLOBAL .PARAM Source Netlist Device models .SUBCKT Netlist .ENDS Output format .ALTER Netlist .END

File Structures and Syntax 6 Groups ■Title ■Source ■Control Items ■Netlist ■Models End File

File Structures and Syntax  6 Groups Title Source Control Items Netlist Models End File

Control Statements ■.OPTION options ■.END[Any comment] .IC V(nod1)=val1 [V(nod2)=val2 ... ■.PARAM parname:=val1 [parname2=val2 ... .GLOBAL node1 [node2 ... .INCLUDE 'filename .TEMP temprature

Control Statements  .OPTION options  .END [Any comment]  .IC V(nod1) =val1 [V(nod2)=val2 …]  .PARAM parname=val1 [parname2=val2 …]  .GLOBAL node1 [node2 …]  .INCLUDE „ filename‟  .TEMP temprature

Library Statement LIB library call statement ■.lib‘filename'entryname .endl entryname .INCLUDE statement

Library Statement  .LIB library call statement .lib „filename‟ entryname .endl entryname .INCLUDE statement

Element Statement elname Cstring n+n-Cval [IC=Vval] Capacity ■Rstring n+n-Rval Resistor Mstring nd ng ns [nb]mname [L=val][W=val][AD=val]+...... MOSFET Dstring n+n-mname [AREA=val][OFF][IC=vd][M=val] Diode Jstring nd ng ns [nb]mname [L=val][W=val][VDS=val]+...... JFEF

Element Statement elname +  Cstring n+ n- Cval [IC=Vval] Capacity  Rstring n+ n- Rval Resistor  Mstring nd ng ns [nb] mname [L=val][W=val][AD=val]+… … MOSFET  Dstring n+ n- mname [AREA=val][OFF][IC=vd][M=val] Diode  Jstring nd ng ns [nb] mname [L=val][W=val][VDS=val]+… … JFEF

Source Statement Vstring n+n-[[DC=]dcval][tranfun][[AC=acmag]acphase] Independent voltage source Istring n+n-[[DC=]dcval][tranfun][[AC=acmag]acphase] Independent current source EX:VIN in 0 PULSE 0 5 2NS 2NS 2NS 30NS 80NS vl 0 v2 pw td tr per

Source Statement Vstring n+ n- [[DC=] dcval][tranfun][[AC=acmag]acphase] Independent voltage source Istring n+ n- [[DC=] dcval][tranfun][[AC=acmag]acphase] Independent current source EX: VIN in 0 PULSE 0 5 2NS 2NS 2NS 30NS 80NS