《EDA技术》课程授课教案（讲稿）第6章 QUARTUSii宏功能模块应用

第6章宏功能模块应用6.1流水线乘法累加器设计MULTOclockCLKOLTITSUM15.0]dataalz.01sultl15.0databiz.01mutiplicatiorthADDEROO21台dataal150lesultr15.01clockEA+Edatab/15.0]1lo 2eoninst:MULTOclockdataalz.01OTPTTou15.0DATAa(7.0]atab[7.0DATAb[7.0]图6-1流水线乘法累加器顶层设计6.1.2电路结构与工作原理1.调用乘法器SymholLibraries:d/altera60/quartus60/ibraies/MegaWizard Plug-In Manager [page 1]TheMegawizardPluginManagerhelpsy00designflesthatcontancustomvariationsofmegafunctioWhicdo youwant toperfom?0Createanew.custommegalunctionvanalionCEdtan existing.custommeoafunctionvariatiorhenvanshnpuicht21991-2006AteaCorporatiocmRepeat-insertmodeanInseltsymbolasbleCarncel图6-2定制新的宏功能块1

1 第 6 章 宏功能模块应用 6.1 流水线乘法累加器设计 6.1.1 电路结构与工作原理 图 6-1 流水线乘法累加器顶层设计 6.1.2 电路结构与工作原理 1. 调用乘法器 图 6-2 定制新的宏功能块

xMegawizard Plug-In Manager [page 2a]Which megafunction would you like to customize?Which device family will you beCyclone ll一using?Select a megafunction from the list belowWhich type of output file do you want to create?InstalledPlug-Ins4AlteraSOPCBuilderCAHDLArithmeticOVHDLALTACCUMULATEE5Verilog HDLALTFP_ADD_SUB?ALTFP_MULTBrowse....What name do you want for the qutput file?ALTMEMMULTD:MULADDMULTOALTMULT_ACCUM (MAC)ALTMULT_ADDALTSQRTGenerate clearbox netlist file instead of a default wrapper fileLPM_ABS[fotusewith supported EDA synthesis tools onl)]LPM_ADD_SUBRetun tothispagefor another createoperationLPMCOMPARELPMCOUNTERNote:Tocompileaprojectsuccessfully intheQuartusllsoftwareyour design files must be in the project directory.in the global userLPM_DIVIDElibranes specified in the Options dialog box (Toolsmenul,or a userLPM MULTlibrayspecifiedin the User Libraries pageoftheSettings dialogPARALLELADDbox (Assignments menu)GatesYour cunent user library directories are由1/0xMegawizardPlug-InMaMULT[page1of5]DNM:LPM MULTVersion 6.0AboutDocumentationParameter2sinBsunmaySettingsLtatGeneral>PipeliningSeneral2Multiplier configurationMULTOMultiplydataa inputby'databinputdataa[7.0]Multiply'dataainput by itself (squaring operation)resut[15.0]Ttedatab[7.0]multiplioation8How wide should the'dataa'input bus be?bits8bitsHow wide should the'datab'input bus be?Create a'sum'input bus withawidth ofVbitsHow should the width of the'result'output be determined?OAutomatically calculate the width16Restrictthe widthtovbitsResource Usage117lutCancelFinish图6-4设置乘法器参数2

2 图 6-3 选择 LPM 宏功能模块 图 6-4 设置乘法器参数

Does the'datab'input bus have a constant value?MULTOONocataa[7.0]0Yes,the value isesut[15.0]datab[7.0]Which type of multiplication do you want?UnsignedSignedWhichmultiplier implementation should be used?Use the default implementation Use dedicated multiplier circuitry (Not available for all families)OUselogicelementsDo you want to pipeline the function?MULTOONoclock2O Yes, I want an output latency ofclock cyclesdataa[7..0]resut[15.0]Create an asynchronous Clear inputdatab[7..0]sionemultiplicatiorCreate a Clock Enable inputWhich type of optimizationdo you want?DefaultOSpeedOAreaXMegawizard Plug-InMLPM_ADD_SUB[page1of6]LPMADDSUB艺Version 6.0AboutDocumentation2.调Parameter2535maryLibrarySettingsHGeneralGeneral2PortsPipeliningVCurrently selected device family:Cyclone IIADDEROdataa[15.0]resu15.01How wide should the'data and'datab'input buses be?16 bits+datab[15.0]Which operating mode do you want for the addet/subtractor?Addition.onlySubtraction onlyCreate an 'add sub'input port to allow me to do both(1 adds; 0 subtracts)n

3 图 6-5 设置乘法器结构类型 图 6-6 将 LPM 乘法器设置为流水线工作方式 2. 调用加法器和锁存器

ADDEROdataa[15.0]Is the'dataa'or'datab'input bus value a constant?resut[15.0]A+BONo,both yalues varydatab[15..0]Yes, dataa=Yes, datab ADDERODo you want any optional inputs or outputs?dataa[15.0]Input:resut[15.0]Createa carry inputdatabl15.0]OutputscoutCreate a Carry outputCreateanoverflowoutputADDERODo you want to pipeline the function?dataa[15..0]clockresut[15.0]Nodatab[15.0]Yes,I want an output latencyofClock cyclescoutCreate an asynchronous Clear nputCreate a Clock Enable inputLPMFFVersion 6.0AboutDocumentationParameter2SimulationsummarySettingsLibraryPageGeneralOptional Inputs8How many flipflops do you want?REGODFFdata[7.0]whichtype of flipflops do youwant?>clockq[7.0]ODFflipflopTflipflopUse'data' input port (acts as abitwise enableifno load signal isused)Create a Clock Enable input4

4 图 6-7 设置 LPM 加法器类型 图 6-8 选择加法器数据输入类型 图 6-9 为加法器增加进位输出 图 6-10 为加法器增加流水线功能

Successful - Thu AueFlow StatusQuartus II Version6.0Bui1d20206/20MULTADDRevision Name6.1.3电路Top-level Entity HameMULTADDFamilyCyelone IIDeviceEP2C8Q208C8FinalTiming ModelsYesMet timing requirements223/8,256（38）Total logic elements127Total registers34/138（25%）Total pins0Total virtual pins0/165,888（0%)Total memory bitsEmbedded Multiplier 9-bit elements0/36(0%）Total PLLs0/2(0%)MULTADD.dfCompilation Report-Timing Analyzer Sum...Timing Analyzer SummaryCompilation Report鲁旨 Legal NoticeRequiredActualSlackTypeFromTimeTimeFlowSummary1N/ADATAb[2]Worst-case tsuNone10.350nsFlowSettingsEEFlowNon-DefautGlobal S2N/A9.806nsADDEROinWorst-case tcoNoneFlowElapsedTime3N/ADATAa[14]Worst-case thNone-1.231 ns自FlowLogN/AClock Setup: CLK'None140.90 MHz [ period = 7.097 ns ) MULT0:instEAnalysis &SynthesisSTotal number of failed paths由营FitterAssembler Timing Analyzer5SummarySettingsSirMULTADD.bdfCompilation Report·TimingA...MULTADD.wf三Timing Analyzer SummalCompilation Report鲁旨 Legal NoticeRequredActualSlackTypeFromTimeTimeEFlowSummaryAWorst-case tsuN/A8.809nsDATAa[NoneFlowSettingsFlowNon-Defaut Global2N/ANone8.981nsADDERWorst-case tcoFlowElapsed Time3Worst-case thN/ANone0.829 nsDATAbl雪FlowLogN/AClock Setup.'CLKNoneRestricted to 180.57MHz(period =5.538 ns)REG0:irREAnalysis &Synthesis5Total numberoffailed paths台FitterO巨Assembler Timing AnalyzerS具SummarySettingsClockSettingsSumm5

5 图 6-11 为 LPM 寄存器选择 D 触发器类型 6.1.3 电路时序仿真与测试 图 6-12 基于逻辑宏单元的设计报告 图 6-14 基于逻辑宏单元的流水线乘法累加器时序分析报告

PoinerMaster Time Bar19.87 usIntervat19.86 usStat12.85ms5.120510.24u515.360520.4805PS25.6us30.72 us35.84 usNane12.85nsLCLX国DATAa16D2323国DATAb0231COUT国Sul3456906816727424401GNDIN[D]D[D]1Y11A1?XDINTD[1]1Y21A2*￥DIN2]0[2]1Y31A3?XDINGD[3]1Y41A4++2GNaDIN[4]D[4]2Y12A1XXDIN[5]D[5]2A22Y2XDINGD[6]2A32Y3*DINDIDIN[7.0]2Y42A4DINZ.APTinst2OCTALBUFWURENWEUTRAMOD[7..0]OUTPUT>07.0]CNT10B+data[7.0]g[7..0]up counterwrenCLK>clockq[9.0]address[9.0]clk_eninclockCLKENinclockeninst1CLRMegaWizardPlug-InManager[page2a]xWhichmegafunctionwouldyou lketo customze?Whichdevicefamiywill youbeCyclone II-nnSelectamegafunction from thelist belowWhichtypeofoutputfiewanttocreate Instaled Plug-InsAltera SOPC BuilderCAHDLAnithmeticCYHDL电国GatesCVerilogHDLa1/0Memory ComplerWhat name do you want for the gutput.tile?Brouse...sshLoeaD:NDATAPIC\RAMOSerialFlashLoadeSignalT ap Il Logic AnalyzerGenerateclaarboxnetist fle insteadof adefautwapperfileShroAALT3PRAM[lor use with supported EDA synthesis tools ontALTCANReturn to this page for another create operationALTQPRANALTSHIFT_TAPSNote.To compessfullyintheQuatusltoft1电52ALTSYNCRAMLPM_FFof the Settingsdialog3000LPMFIFO+box (Assigrments menu),LPMLATCHYourcurentuserlbtarydirectotiesareLPM_RAM_DPLPMRAMDPOMBOAFIJTAGastotanrRaNexts6

6 图 6-15 基于专用嵌入式乘法器模块的流水线乘法累加器时序分析报告 图 6-16 MULTADD 工程仿真波形 6.2 逻辑数据采样电路设计 图 6-17 逻辑数据采样电路顶层设计

MegawizardPlug-In Manager-LPM_RAM_DQ [page3of 7]x.LPM_RAM_DQ之Version6.0AboutDocumentationParamete2simdshion31sumSettingSWikkkeVCurrently selected device familyCyclone1IRAMO9[7.0]data[7.0]wrenaddress[9.0]8bitsHow wide should the'q'output bus be?inclock1024How many 8-bit words of memory?wordsV>outclockWhat should the RAM block type be?M4KOAutoOM512Optionsi..OM-RAMLCsAutoSet the maximum block depth towordsWhatclockingmethodwouldyoulketouseSingle clockODual clock:use separate'nput'andoutput'clocksResource Usage2M4KCancelEinishWhich ports should be registered?RAMOdata'andwreninputdata[7.0]c[7.0]address input portwreng outputportaddress[9.0]>inclockinclocken Create one clock enable signal for eachclock signal.All registeredports areMoreOptionscontrolled by the enable signal(s).Create a byte enable port8vbitsWhatis the width of a bytefor byte enable? Create an 'aclr asynchronous clearMore Options...for the registered portsDo you want to specify the initial content of the memory?RAMONo,leave itblankdata[7.0]q(7.01 Initialize memory content data to xX.X on power-up in simulatiorwrenaddress[9.0]es, usethisfileforthememorycontentdatainclock(You can use a Hexadecimal (Intel-format) File [.hex] or a Memor)inclockenInitialization File [.mif]Browse...Filename!TheinitialContentfileshouldconfomVto which port's dimensions?Allow In-System Memory Content Editor to capture and update contentindependently of the system clockRAM1]Resource UsageThe 'Instance ID' of this RAM is:2M4K+1sid_mod_ram_romEinishCancel7

7 图 6-18 调用 LPM RAM 宏功能模块 图 6-19 LPM RAM 参数设置 图 6-20 增加时钟使能控制

Which type of output file do you want to create?Installed Plug-InsAltera SOPC BuilderCAHDLArthmeticOVHDLALTACCUMULATECVerlog HDLALTFPADDSUBALTFP_MULTBrowse....What name do you want for the gutputfle?ALTMEMMULTD:ADATAPICICNT10BALTMULT_ACCUM [MAC)ALTMULT_ADDGenerate clear box netlist file instead of a default wrapperfleALTSQRTLPM_ABS(for use with supported EDA synthesis tools only)1LPM_ADD_SUBReturn to this page for another create operationLPM_ COMPARELPM_COUNTERNote:TocompileaprojectsuccessfulyintheQuartusll software,方your design files must be in the project directory, in theglobal userLPM_DIMIDEJnJTxMegaWizard Plug-InManager-LPM_COUNTER[page3of 7]LPM COUNTERVersion6.0AboutDocumentationParameter2Siulation3summarySettingsLibrarGeneralGeneral2>OptionalInputsCNT10B10MbitsHow wide should the'q'output bus be?up counterclockq[9.0]What should the counter direction be?OUp.onlyDownonlyCreatean'updown'inputporttoallowmetodo both[1 countsup,0 countsdown]CNT10BWhich type of counter do you want?upoounterPlainbinary>clockOModulus,witha countmodulus ofq[9.0]clk_enDo you want any optional additional ports?MClockEnableCarry-inCountEnableCarry-out8

8 图 6-21 允许在系统存储器内容编辑器能对此 RAM 编辑 图 6-22 调用 LPM 计数器 图 6-23 设置为加法计数器

Doyouwantanyoptionalinputs?CNT10BupcountenSynchronous inputsAsynchronous inputs>clockc[9.0]clk_enClearClear0LoadLoadSetSetOSet toall 1'sOSettoal 1'sSettoOSettoDxSettings-DPICCategory.GeneralDefault ParametersFles User Libraries (Current Project)Specity the default settings for the parameters used in your project Assignments in design files orassignments made in the Assignment Editorwilloverridethesedefaults,DeviceTimingAnalysisSettingsEDA Tool SetingsParameterAdd白CompilationProcessSettingsCYCLONEILSAFEWRITEName. Early Timing E stimateDelete. IncrementalCompilation"VERIFIED_SAFE"Defaut setting:TimingAnalysisProcessingAnalysis&Synthesis Setings HDLInputExistingparametersetings Verilog HDL InputName:SettingDefault ParametersSynthesis Netlist Optimizations*-Fitter SettinosParameterChangeCYCLONEIL_SAFE_WRITEName:DeleteVERIFIED SAFEDefault setting:Existingparameter settings:Name:SettingCYCLONEIL SAFEW..."VERIFIED SAFE"9

9 图 6-24 设置为二进制计数器 图 6-25 增加异步清 0 控制 图 6-26 键入默认参数

因627加入斗公46.Pps5.124810.24 us15.38s20.489825.0 us30.72 s35.84 540.9808Hane12.85 nsCLX:CLCENCLRWRENBDIN0008[?]FrrewnnnnnnnwnnnW[5]UuU008[4I排[3]8(2]DIW1]LaINCoD93星多多多多装部muuu0000000000000n0000000000000000000000000000000000000000uuuuuuni1LLoto)图6-28逻辑数据采样电路时序仿真波形6.3在系统存储器数据读写编辑器应用1.锁定引脚PinCategory:This cell specifies the name of the I/Edit:XVEToLocationDDCLKPIN_23CLK_ENPIN_81DCLRPIN_101APIN_67DDIN[O]DDIN[]PIN_694图6-29引脚锁定DIN[2]PIN721DIN[3]PIN_7544DIN[4]PIN_77DIN[5]PIN_814DIN[6]PIN_824DINE7]PIN_864Q[0]PIN_684DQ1]PIN_70Q[2]PIN_744Q[3]PIN_76+Q[4]PIN_804?Q[5]PIN_844Q[6]PIN_874DQ[7]PIN_894DWRENPIN_111>10

10 图 6-27 加入默认参数 图 6-28 逻辑数据采样电路时序仿真波形 6.3 在系统存储器数据读写编辑器应用 1. 锁定引脚 图 6-29 引脚锁定