电子科技大学：《数字系统EDA技术》第三章（3-9） 基本逻辑电路设计

§39基本逻辑电路设计 基本逻辑电路 组合逻辑电路 时序逻辑电路 组合逻辑电路设计 简单门电路、编码器、译码器 加法器、多路选择器、三态门等

1 基本逻辑电路： 组合逻辑电路、 时序逻辑电路 一 组合逻辑电路设计 简单门电路、编码器、译码器、 加法器、多路选择器、三态门等。 §3.9 基本逻辑电路设计

1、基本门电路 Ibrary leeei se ieee std logic 1164. alli ntity gate is port(a, b: in std logici yand, yor, nand, nor, ynot, yxor: out std logic) nd gate rchitecture art of gate is egin yand<=a and b yor<=a or bi anand<=a nand bi nor<=a nor bi ynot<=not bi yxor<=a xor bi nd arti 2

2 1、基本门电路

2、编码器 设计一个8输入优先级编码器,yo级别最低 y7级别最高:输出为3位编码。 Y7=1 Vec=111 pR工oR工TY Y6=1 Ⅴec=110 y1 Y5=1Vec=101 Y4= y三 ec[2· Ⅴec=100 4 Y3 Vec=011 y Y2 Vec=010 了 Y1=1 Vec=001 Y0=1 Vec=000

3 2、编码器 设计一个 8 输入优先级编码器，y0 级别最低， y7 级别最高；输出为3位编码。 Y7=1 Vec=111 Y6=1 Vec=110 Y5=1 Vec=101 Y4=1 Vec=100 Y3=1 Vec=011 Y2=1 Vec=010 Y1=1 Vec=001 Y0=1 Vec=000

方法1:利用多选择语句自顶向下的优先特性 library ieee use ieee std logic 1164.all entity priority is port(signal yo, y1, y2,y3, y4, y5, y6,y7:in std logici signal vec: out std logic vector (2 downto 0))i end priority. architecture behavior of priority is begin process(yo, yl, y2, y3,y4, y5, y6,y7 begin if (y7=1)then vec<=111"i elsif (y6='1')then vec<=110 i elsif (y5=1)then vec<=101 i elsif (y4=1)then vec<=100 i elsif (y3=1)then vec<=011 i elsif (y2='1)then vec<=010i elsif (yl=1)then vec<=001i elsif (yo=f1')then vec<=000 i end ifi end processi end behavior

4 方法1：利用 if 多选择语句自顶向下的优先特性

方法2:进程内为顺序语句,最先描述优先级最低 最后描述优先级最高,可实现优先级编码。 library ieee use ieee std logic 1164.all entity priority is port(signal yo, yl, y2, y3, y4, y5, y6, y7: in std logic signal vec: out std logic vector(2 downto 0))i end priority氵 architecture behavior of priority is begin process(yo, yl, y2, y3, y4, y5,y6,y7) beqir if (yo=1)then vec<=000 end if if (yl=1)then vec<=001 end ifi if (y2=f1') then vec<=001 end if if(y3=1)then vec<=011; end ifi if (y4=1) then vec<=100 i end ifi if (y5=1)then vec<=101i end ifi if (y6=1)then vec<=110; end if if (y7=1)then vec<=11l i end ifi end process end behavior

5 方法2：进程内为顺序语句，最先描述优先级最低， 最后描述优先级最高，可实现优先级编码

方法3:利用条件赋值语句 architecture behavior of priority is begin vec <=111 when y7=1 else 110 when y6=else 4101” when y5=1else 100 when y4=else 011” when y3=1'else 010 when y2=else 001 when y1=else 0002 when y0= 1'else XXX” end behavior

6 方法3：利用条件赋值语句 architecture behavior of priority is begin vec <= “111” when y7 = ‘1’ else “110” when y6 = ‘1’ else “101” when y5 = ‘1’ else “100” when y4 = ‘1’ else “011” when y3 = ‘1’ else “010” when y2 = ‘1’ else “001” when y1 = ‘1’ else “000” when y0 = ‘1’ else “XXX”; end behavior;

3、译码器 译码器是编码器的逆过程。如3-8译码器 sel=000Y=00000001 Sel=001Y=00000010 DEC sel=010Y=00000 seL[2。]y[7。 sel=011Y=00001000 sel=100Y=00010000 sel=101Y=00100000 sel=110Y=01000000 sel=111Y=10000000

7 3、译码器 译码器是编码器的逆过程。如 3-8 译码器： sel=000 Y=00000001 sel =001 Y=00000010 sel =010 Y=00000100 sel =011 Y=00001000 sel =100 Y=00010000 sel =101 Y=00100000 sel =110 Y=01000000 sel =111 Y=10000000

方法1:使用逻辑左移运算符 library leee use ieee std logic 1164. all use ieee std logic unsigned. all entity decoder is port(inp: in std logic vector(2 downto 0 outp: out std logic vector(7 downto O)) end decoder architecture rtl of decoder is begin outp<=00000001 sll(conv integer(inp)) end rtl

8 方法1：使用逻辑左移运算符 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is port(inp : in std_logic_vector(2 downto 0); outp : out std_logic_vector(7 downto 0)); end decoder; architecture rtl of decoder is begin outp<=“00000001” sll(conv_integer(inp)); end rtl;

方法2:使用 processi语句 library ieee use ieee std logic 1164. all use ieee std logic unsigned. all entity decoder is port(inp: in std logic vector(2 downto 0 outp: out std logic vector(7 downto O)) end decoder architecture rtl of decoder is begin process(inp) begin outp0) outp( conv integer(inp)-="1 end process end rtl

9 方法2：使用process语句 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is port(inp : in std_logic_vector(2 downto 0); outp : out std_logic_vector(7 downto 0)); end decoder; architecture rtl of decoder is begin process(inp) begin outp’0’); outp(conv_integer(inp))<=‘1’; end process; end rtl;

方法3:使用case语句实现。 library ieee; use ieee std logic 1164.all entity dec is port (sel: in std logic vector(2 downto 0)i en: in std logici out std logic vector(7 downto 0) end dec: architecture behavior of dec is begi

10 方法3：使用 case 语句实现