电子科技大学：《射频集成电路 RF Integrated Circuits》课程教学资源（课件讲稿）第二讲 CMOS器件

第二讲 CMOS器件 游飞博导，副教授 电子科学与工程学院，feiyou@uestc.edu.cn 22西/

2020/3/7 1 第二讲 CMOS器件 游飞 博导，副教授 电子科学与工程学院, feiyou@uestc.edu.cn

Transistor Transistor stands for .. Transistor are semiconductor devices that can be classified as -Bipolar Junction Transistors (BJTs) Field Effect Transistors(FETs) Depletion-Mode FETs or(e.g.,JFETs) Enhancement-Mode FETs(e.g.,MOSFETs) 西7

2020/3/7 2 SM 11 EECE 488 ± Set 1: Introduction and Background Transistor ‡ Transistor stands for « ‡ Transistor are semiconductor devices that can be classified as ± Bipolar Junction Transistors (BJTs) ± Field Effect Transistors (FETs) ‡ Depletion-Mode FETs or (e.g., JFETs) ‡ Enhancement-Mode FETs (e.g., MOSFETs)

Simplistic Model MOS transistors have three terminals:Gate,Source,and Drain Gate Souw,六an The voltage of the Gate terminal determines the type of connection between Source and Drain (Short or Open). Thus,MOS devices behave like a switch NMOS PMOS Ve high Device is ON Device is OFF D is shorted to S D S are disconnected Ve low Device is OFF Device is ON D &S are disconnected D is shorted to S 2西3/7

2020/3/7 3 SM 12 EECE 488 ± Set 1: Introduction and Background Simplistic Model ‡ MOS transistors have three terminals: Gate, Source, and Drain ‡ The voltage of the Gate terminal determines the type of connection between Source and Drain (Short or Open). ‡ Thus, MOS devices behave like a switch Device is ON D is shorted to S Device is OFF D & S are disconnected VG low Device is OFF D & S are disconnected Device is ON D is shorted to S VG high NMOS PMOS

Physical Structure 1 。 Source and Drain terminals are identical except that Source provides charge carriers,and Drain receives them. MOS devices have in fact 4 terminals: Source,Drain,Gate,Substrate (bulk) Q Metal D Source (S) Gate (G) Drain (D) 0 0 Q Oxide (SiO2) Metal Oxide (SiO2) (thickness fax) Source region Channel n n region -L p-type substrate p-type substrate (Body) (Body) Channel region B Body Drain region (B) (a) (b) Microelectronic Circuits,2004 Oxford University Press 心2西/

2020/3/7 4 SM 13 EECE 488 ± Set 1: Introduction and Background Physical Structure - 1 ‡ Source and Drain terminals are identical except that Source provides charge carriers, and Drain receives them. ‡ MOS devices have in fact 4 terminals: ± Source, Drain, Gate, Substrate (bulk) © Microelectronic Circuits, 2004 Oxford University Press

Physical Structure -2 Charge Carriers are electrons in NMOS devices,and holes in PMOS devices. 。 Electrons have a higher mobility than holes So,NMOS devices are faster than PMOS devices We rather to have a p-type substrate?! G Poly Oxide Lp:Due to Side Diffusion Poly-silicon used instead of Metal for fabrication reasons p-substrate drawn -Lo Actual length of the channel (Lef)is less than the length of gate 西/7

SM2020/3/7 5 14 EECE 488 ± Set 1: Introduction and Background Physical Structure - 2 LD: Due to Side Diffusion Poly-silicon used instead of Metal for fabrication reasons ‡ Actual length of the channel (Leff) is less than the length of gate ‡ Charge Carriers are electrons in NMOS devices, and holes in PMOS devices. ‡ Electrons have a higher mobility than holes ‡ So, NMOS devices are faster than PMOS devices ‡ We rather to have a p-type substrate?!

Physical Structure-3 N-wells allow both NMOS and PMOS devices to reside on the same piece of die. n-substrate (a) p-substrate (h) As mentioned,NMOS and PMOS devices have 4 terminals: Source,Drain,Gate,Substrate (bulk) In order to have all PN junctions reverse-biased,substrate of NMOS is connected to the most negative voltage,and substrate of PMOS is connected to the most positive voltage. 4西/d 6

2020/3/7 6 SM 15 EECE 488 ± Set 1: Introduction and Background Physical Structure - 3 ‡ N-wells allow both NMOS and PMOS devices to reside on the same piece of die. ‡ As mentioned, NMOS and PMOS devices have 4 terminals: Source, Drain, Gate, Substrate (bulk) ‡ In order to have all PN junctions reverse-biased, substrate of NMOS is connected to the most negative voltage, and substrate of PMOS is connected to the most positive voltage

Physical Structure -4 MOS transistor Symbols: NMOS PMOS NMOS PMOS NMOS PMOS D D D Go- …0B (a) (b) (e】 。In NMOS Devices:Source-cleciron→Drain Current flows from Drain to Source ·In PMOS Devices:Source-_hoe→Drain Current flows from Source to Drain 。 Current flow determines which terminal is Source and which one is Drain.Equivalently,source and drain can be determined based on their relative voltages. 西/

2020/3/7 7 SM 16 EECE 488 ± Set 1: Introduction and Background Physical Structure - 4 ‡ MOS transistor Symbols: ‡ In NMOS Devices: Current flows from Drain to Source ‡ In PMOS Devices: Current flows from Source to Drain ‡ Current flow determines which terminal is Source and which one is Drain. Equivalently, source and drain can be determined based on their relative voltages. Source Drain electron o Source Drain hole o

Threshold Voltage -1 Consider an NMOS:as the gate voltage is increased,the surface under the gate is depleted.If the gate voltage increases more, free electrons appear under the gate and a conductive channel is formed. 40.1V 40.1V +0.1V n p-substrate p-substrate Negative lons b +0.1V +0.1V p-substrate p-substrate Electrons c (a)An NMOS driven by a gate voltage,(b)formation of depletion region,(c)onset of inversion, and(d)channel formation As mentioned before,in NMOS devices charge carriers in the channel under the gate are electrons. 2西7

2020/3/7 8 SM 17 EECE 488 ± Set 1: Introduction and Background Threshold Voltage - 1 (a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion, and (d) channel formation ‡ Consider an NMOS: as the gate voltage is increased, the surface under the gate is depleted. If the gate voltage increases more, free electrons appear under the gate and a conductive channel is formed. ‡ As mentioned before, in NMOS devices charge carriers in the channel under the gate are electrons

Threshold Voltage -2 Intuitively,the threshold voltage is the gate voltage that forces the interface(surface under the gate)to be completely depleted of charge (in NMOS the interface is as much n-type as the substrate is p-type) Increasing gate voltage above this threshold (denoted by VTH or V) induces an inversion layer(conductive channel)under the gate. Gate electrode Induced G n-type D Oxide (SiO,) channel p-type substrate Depletion region 专 Microelectronic Circuits,2004 Oxford University Press 心2西月日

2020/3/7 9 SM 18 EECE 488 ± Set 1: Introduction and Background Threshold Voltage - 2 ‡ Intuitively, the threshold voltage is the gate voltage that forces the interface (surface under the gate) to be completely depleted of charge (in NMOS the interface is as much n-type as the substrate is p-type) ‡ Increasing gate voltage above this threshold (denoted by VTH or Vt ) induces an inversion layer (conductive channel) under the gate. © Microelectronic Circuits, 2004 Oxford University Press

Threshold Voltage -3 Analytically: %m=s+2-m+2 Where: ΦMs=Built-in Potential=Φgate-Silicon the difference between the work functions of the polysilico n gate and the silicon substrate Work Function (electrostaticpotentiai)-K n. Qn=Charge in the depletion region=V4:q:s。·Φ，N 西/司 10

2020/3/7 10 SM 19 EECE 488 ± Set 1: Introduction and Background Threshold Voltage - 3 Analytically: ox dep TH MS F C Q V )  2 )  Where: the polysilicon gate and the silicon substrate the difference between the work functions of Built -inPotential )MS )gate  )Silicon ¸ ¸ ¹ · ¨ ¨ © § ) i sub F n N q K T Work Function (electrostatic potential) ln Qdep q si F Nsub Charge in the depletion region 4 H )