清华大学：Interconnect Parasitic Extraction（PPT讲稿）

Interconnect Parasitic Extraction Speaker: Wenjian Yu singhua University, Beijing, China Thanks to J. White, A Nardi, W. Kao, L. T. Pileggi, Zhenhai zhu

Interconnect Parasitic Extraction Speaker: Wenjian Yu Tsinghua University, Beijing, China Thanks to J. White, A. Nardi, W. Kao, L. T. Pileggi, Zhenhai Zhu

Outline ntroduction to parasitic extraction Resistance extraction Capacitance extraction Inductance and impedance (RlC) extraction

2 Outline ◼ Introduction to parasitic extraction ◼ Resistance extraction ◼ Capacitance extraction ◼ Inductance and impedance (RLC) extraction

Introduction to Parasitic Extraction

3 Introduction to Parasitic Extraction

ntroduction a Interconnect: conductive path Ideally: wire only connects functional elements (devices, gates, blockS,.and does not affect design performance a This assumption was approximately true for Large 'design it is unacceptable for dsm designs Slides courtesy A Nardi, UC Berkeley

4 Introduction ◼ Interconnect: conductive path ◼ Ideally: wire only connects functional elements (devices, gates, blocks, …) and does not affect design performance ◼ This assumption was approximately true for “large” design, it is unacceptable for DSM designs Slides courtesy A. Nardi, UC Berkeley

Introduction ■ Real wire has 口 Resistance a Capacitance □ nductance a Therefore wiring forms a complex geometry that introduces capacitive, resistive and inductive parasitics. Effects a Impact on delay, energy consumption, power distribution a Introduction of noise sources, which affects reliability To evaluate the effect of interconnects on design performance we have to model them Slides courtesy A Nardi, UC Berkeley

5 Introduction ◼ Real wire has:  Resistance  Capacitance  Inductance ◼ Therefore wiring forms a complex geometry that introduces capacitive, resistive and inductive parasitics. Effects:  Impact on delay, energy consumption, power distribution  Introduction of noise sources, which affects reliability To evaluate the effect of interconnects on design performance we have to model them Slides courtesy A. Nardi, UC Berkeley

Conventional Design Flow Funct. Spec RTL Behar. Simul Logic Synth Stat. Wire model Front-end Gate-level Net Gate-Lev Sim Back-end floorplanning Parasitic Extrac Place route Layout Slides courtesy A Nardi, UC Berkeley

6 Conventional Design Flow Funct. Spec Logic Synth. Gate-level Net. RTL Layout Floorplanning Place & Route Front-end Back-end Behav. Simul. Gate-Lev. Sim. Stat. Wire Model Parasitic Extrac. Slides courtesy A. Nardi, UC Berkeley

From electro-magnetic analysis to circuit simulation Parasitic extraction Electromagnetic analysis Filament Panel with 0 with uniform uniform charge current Model order Thousands ofr l, c reduction Reduced circuit

7 From electro-magnetic analysis to circuit simulation Parasitic extraction / Electromagnetic analysis Thousands of R, L, C Filament with uniform current Panel with uniform charge Model order reduction Reduced circuit

Challenges for parasitic extraction ■ Parasitic Extraction DAs design get larger, and process geometries smaller than 0.35um, the impact of wire resistance, capacitance and inductance(aka parasitics) becomes significant a Give rise to a whole set of signal integrity issues a Challenge o Large run time involved(trade-off for different levels of accuracy) a Fast computational methods with desirable accuracy

8 Challenges for parasitic extraction ◼ Parasitic Extraction As design get larger, and process geometries smaller than 0.35m, the impact of wire resistance, capacitance and inductance (aka parasitics) becomes significant Give rise to a whole set of signal integrity issues ◼ Challenge Large run time involved (trade-off for different levels of accuracy) Fast computational methods with desirable accuracy

Resistance extraction

9 Resistance Extraction

Outline a Introduction to parasitic extraction Resistance extraction a Problem formulation D EXtraction techniques Numerical techniques a Other issues a Capacitance extraction nductance and rlc extraction 10

10 Outline ◼ Introduction to parasitic extraction ◼ Resistance extraction Problem formulation Extraction techniques Numerical techniques Other issues ◼ Capacitance extraction ◼ Inductance and RLC extraction