电子科技大学：《VHDL语言与数字集成电路设计》数字逻辑3-2

Electrical behavior of cmos Steady-state behavior when output is hold on 1 or o Dynamic behavior when output is changing

Steady-state behavior when output is hold on 1 or 0 Dynamic behavior when output is changing Electrical behavior of CMOS

The electric model for mos transistor 大Ron大 D G S B G Cg B Cs Ron =Cd Cg: gate capacitor Cd and cs: junction capacitors Ca≈Cs≈3Cg

The electric model for MOS transistor Cg: gate capacitor Cd and Cs: junction capacitors Cd  Cs  3Cg

The electric model for basic cmos circuit Rp G D FⅩ F G g Cd Rn Input capacitor: related to gates; Output capacitor: related to junctions; Output resistor: related to the gate area

The electric model for basic CMOS circuit Input capacitor: related to gates; Output capacitor: related to junctions; Output resistor: related to the gate area

The electric model for basic cmos circuit Vcc P net Rp R p input utput N net Rnl Co Co Gnd When state is hold, only r is considered Some voltage must be fallen on r

When state is hold, only R is considered ; Some voltage must be fallen on R ! The electric model for basic CMOS circuit

Steady-state behavior for inverter vout out DD DD Ideal behavior Real behavior The input between Vi and vi should be avoid

Steady-state behavior for inverter Ideal behavior Real behavior The input between VIL and VIH should be avoid !

Logic level and noise margin Out put out CC DD OH noise margIn Abnormal Abnormal IL noise margin LoW OW When load become heaver the noise margin become narrow

Logic level and noise margin When load become heaver , the noise margin become narrow !

Dynamic behavior rRp p Rn R High state Co Co state RnC If the output is changed, the capacitors must be charged or uncharged through a resistor The delay time is decided by rc

Dynamic behavior If the output is changed, the capacitors must be charged or uncharged through a resistor ! The delay time is decided by RC !

How to estimate the time delay for a single device Problem: Rp Rp R and c belong to different devices can R Rn not be decided from Ci Co Ci Co single device Solution Make all the output resistors a same value, the time delay can be decided only b capacitors of the device l

How to estimate the time delay for a single device Problem: R and C belong to different devices , can not be decided from single device ! Solution : Make all the output resistors a same value , the time delay can be decided only by capacitors of the device !

The minimal size device Let the length be the minimal size: all ther and c will be s W 业 decided by the width! R∝(1/W)C∝W For the minimal size nmos B R=R0Cg=CCd≈3C0 Take these values as units i

The minimal size device Let the length be the minimal size; all the R and C will be decided by the width ! R  (1/W) C W Take these values as units ! For the minimal size NMOS: R = R0 Cg = C0 Cd  3C0

The minimal size device The resistivity of Pmos is larger than NMOS, to keep s W r the same value. its width must increase: for the minimal size pmos W=2Cg=C0≈2C0 B R=B0Cd=3g≈6C0 For the minimaInmos set w=l

The minimal size device The resistivity of PMOS is larger than NMOS, to keep R the same value, its width must increase; For the minimal size PMOS : R = R0 0 2C0 Cg = rC  Cd = 3Cg  6C0 W = 2 For the minimal NMOS, set W=1