电子科技大学：《VHDL语言与数字集成电路设计》数字逻辑3-3

How to make a better device Good performance faster and less power consumed Low cost more compact and use less area

How to make a better device Low cost : more compact and use less area ! Good performance : faster and less power consumed !

The time delay and area for the simple device CC Vcc 2/14-4 NOR out n12n/1 out NAND(n) Gnd Gnd =10n+2 A=n+2n t,=1ln+1 n+n

The time delay and area for the simple device t d 10n 2 A n 2n 2 = + = + t d = n + A = n + n 2 11 1 2

Fan-in The input numbers of a single gate When fan-in decrease, the device is better The time delay is proportional to the fan-in t4≈10.n The logic area is proportional to the square of fan-in

Fan-in :The input numbers of a single gate When fan-in decrease, the device is better ! The time delay is proportional to the fan-in ! 10 0 t n t d    The Logic area is proportional to the square of fan-in !

Use parallel design to limit the fan-in RANDL RAND8 nOPA RANDL tx≈84 ≈42+22+12=76 A≈80 A≈48+10+3=6 If the fan-in is greater than 5, it should be instead by parallel circuit

Use parallel design to limit the fan-in If the fan-in is greater than 5 , it should be instead by parallel circuit ! 80 84   A t d 48 10 3 61 42 22 12 76  + + =  + + = A t d

Use parallel design for positive output gate PANDL RAND2 NOP2 AND4 NOP2 oR4 t,≈40+10=50t≈20+20=40 The fan-in should be less than 4 i

Use parallel design for positive output gate  40+10 = 50 t d  20 + 20 = 40 d t The fan-in should be less than 4 !

Use parallel design for AO structures ND3 IAND3 AND-OR Aol-|NV∨ NAND-NAND 14≈60+20=80t4≈84+10=94t4≈30+30=60 A≈52+12=64A≈59+3=614≈(5+8)2=46 The ao structures always implemented by nand-nand structures

Use parallel design for AO structures 59 3 61 84 10 94  + =  + = A t d (15 8) 2 46 30 30 60  +  =  + = A t d The AO structures always implemented by NAND-NAND structures. 52 12 64 60 20 80  + =  + = A t d

CMOS transmission gate and three state gate Three state buffer Three state inverter d≈36 t,≈36 A≈6 A≈15 The r may increase

CMOS transmission gate and three state gate Three state buffer Three state inverter 6 36   A t d The R may increase ! 15 36   A t d

XOR gate Simple multiplexes a f b aba abab f a f f b S a≈36A≈21 Similar as nand(3)!

XOR gate Simple Multiplexes t d  36 A  21 Similar as NAND(3)!

Fan out: input numbers driven by one output FO=3 out interconnect line logic cell Chip logic cel logic ce‖l logic ce‖l in The capacitors of interconnect line are much larger than the capacitors in the logic cells

Fan out : input numbers driven by one output The capacitors of interconnect line are much larger than the capacitors in the logic cells !

Make the driven strength of the output larger x F0=3 out interconnect line logic cell Chip logic cell logic ce‖l logic cell Use inverters as buffer i

Make the driven strength of the output larger Use inverters as buffer !