《EDA技术》实用教程（PPT讲稿）第5章 QuartusII 应用向导

EDA技术实用教程 第5章 Quartus应用向导

EDA 技术实用教程 第 5 章 QuartusII 应用向导

51基本设计流程 51建立工作库文件夹和编辑设计文件 M E Vhdl.d 1 LIBRARY IEEE USE IEEE STD LOGIC 1164. ALL 3 USE IEEE STD LOGIC UNSIGNED ALL A ENTITY CNT10 IS PORT (CLK, RST,EN IN STD LOGIC Hlew 7 COUT OUT s Save As Device Design Files Other Files I EDrQ:保存在①cmum 9 ARCHITECTURI LD BEGIN AHDL Fe PROCESS Block Diagram/Schematic File Quartus II EDIF VARIABI1我最近的文档 3 BEGIN SOPC Builder System IF RS Do you want to create a new project with this file? ELSI 桌面 匚是①否0」取消 图5-1选择编辑文件的语言类型,键入源程序并存盘 K 康芯科技

5.1 基本设计流程 KX 康芯科技 图5-1 选择编辑文件的语言类型，键入源程序并存盘 5.1.1 建立工作库文件夹和编辑设计文件

51基本设计流程 512创建工程 Her Project lizard: Directory, Hame, Top-Level Entity [pag..x What is the working directory for this project? D: CNT10B what is the name of this project? CNT10 What is the name of the top-level design entity for this project? This name is case sensitive and must exactly match the entity name in the design file CNT10 Use Existing Project Settings 图5-2利用“ New preject wizard”创建工程cnt10 K 康芯科技

5.1 基本设计流程 KX 图5-2 利用“New Preject Wizard”创建工程cnt10 康芯科技 5.1.2 创建工程

51基本设计流程 512创建工程 Hew Project izard: Add Files [page 2 of 51 Select the design files you want to include in the project. Click Add All to add all design files in the project directory to the project. Note: you can always add design files to the project later File name Add File name Type AddAll CNT1Owhd VHDL File Remove 图5-3将所有相关的文件都加入进此工程 K 康芯科技

5.1 基本设计流程 KX 图5-3 将所有相关的文件都加入进此工程 康芯科技 5.1.2 创建工程

51基本设计流程 512创建工程 Hew Project Vizard: Family Device Settings [page 3 of 5]x Select the family and device you want to target for compilation Show in Available device list Family: Cyclone ll Package TQFP Target device C Auto device selected by the Fitter Pin count 144 a Specific device selected in 'Available devices' list Speed grade Core voltage: 1.2 v Show Advanced Devices Available devices N ame LE Memor. Embed.PLL EP2C5T144C8 460811980826 EP2C5T1448 4608 11980826 EP2C8T 144C8 8256 16588836 EP2C8T1448 16588835 2222 图5-4选择目标器件EPC5T44c8 K 康芯科技

5.1 基本设计流程 KX 图5-4 选择目标器件EP2C5T144C8 康芯科技 5.1.2 创建工程

51基本设计流程 512创建工程 Convert MAX+PLUS II Project Allows you to convert existing MAXtPLUS II projects and assi gnments into a new Quartus Ii project MAX+PLUS II file name F: /disl5/DM_1K30/ Pk2-1k30/Musicl/SONGER. ACF Quartus II project name SONGER OK Cancel 图55将Max+plus工程转换为 Quartus再工程 K 康芯科技

5.1 基本设计流程 KX 图5-5 将Max+plusII工程转换为QuartusII工程 康芯科技 5.1.2 创建工程

51基本设计流程 513编译前设置 Settings- CHT10 Category General Device User Libraries[ Current Project) Select the family and device you want to target for compilation. +.Timing Analysis Settings + EDA Tool Settings Family: Cyclone ll Show in 'Available devices' list +Compilation Process Settings Package: TQFP Device& Pin Options E] Analysis Synthesis Settings 144 VHDL Input Target device Verilog HDl Input C Auto device selected by the Fitter Default Parameters Specific device selected in ' Available devices' list Core voltage 1.2 Synthesis Netlist Optimizations C Other: n/a y Show advanced devices Physical Synthesis Optimizations Assembler Available devices Design Assistant ame LEs Memor. Embed. PLL ignalT ap ll Logic Analyzer EP2C5T144C8 460811980826 nnrcT14In 图5-6选择目标器件EP2C5T144c8 K 康芯科技

5.1 基本设计流程 KX 图5-6 选择目标器件EP2C5T144C8 康芯科技 5.1.3 编译前设置

51基本设计流程 513编译前设置 Device Pin Options Dual-Purpose Pins Voltage Pin Placemen Er De elect or General Configuration Programming Files Unused pins Specify general device options. These options are not dependent on the configuration scheme Options v Auto-restart configuration after error rElease clears before tri-states Enable user-supplied start-up clock (CLKUSR) DEnable device-wide reset(DEV CLRn □ Enable device-wide output enable[DEE〕 IEnable INIT DONE output Auto usercode JTAG user code(32-bit hexadecimal]: ED32567 图5-7选择配置器件的工作方式 K 康芯科技

5.1 基本设计流程 KX 图5-7选择配置器件的工作方式 康芯科技 5.1.3 编译前设置

51基本设计流程 513编译前设置 Device Pin Options Dual-Purpose Pins Voltage Pin Placement Error Detection cro General Confi gurati on Programming Files Unused pins Specify the device configuration scheme and the configuration device Configuration scheme: Active Serial (can use Configuration Device) Configuration mode: Standard Confiquration device y Use configuration device: EPCS1 Configuration Device Options v Generate compressed bitstreams 图5-8选择配置器件和编程方式 K 康芯科技

5.1 基本设计流程 KX 图5-8 选择配置器件和编程方式 康芯科技 5.1.3 编译前设置

514全程编译 CH Quartus II- D:/cnt 10b/CHT10-CNT10 ile Edit View Project Assignments Processing Tools Window Help D日》 C CNT10 Project Navigator abc cNt10 yhd Compilation Report-Flow Sum Entity Logic Cells LC I △ Cyclone:Ecr4c8 Compilation Report- Flow Summary I L.cnT10 low Sunnary △ Hierarchy B Files Design U回 Flow Status Flow Failed- Sun Sep 25 12: 20: 23 2005 Status Quartus Ii Versi 5.0 Build 168 06/22/2005 SP 1 SJ Full versi I Progress %Time O Revisi on ame T10 Full Compilati 12%00:003 Top-level Entity Name CNT10 Analysis& Synthesis[ 50800:00:03 Cyclone Fitter 0% 00:00:00 Device EP1C3T144C8 Assembler 00:00:00 Timing Analyzer 0%00:000 Quartus II j Full Compilation was NOT successful (3 errors, 0 warnings) 工nfo:冰冰水冰*家****本*率*水*水水水冰水水冰冰 确定 i Info: Running Quartus II Analysis Sy 4 Info: Command: quartus_map -read_settings_files=on --write_settings_files=off CNT10-c CNT10 8 Error syntax error at CNT10 vhd(9) near text"ARCHITECTURE": expecting s Error: VHIL syntax error at CNT10 whd(27): name used in construct must match previously specified name"CNT10 Error: Ignored construct CNT10 at CNT10 vhd (4) because of previous errors 4 Info: Found 0 design units, including 0 entities, in source file CNT10 vhd +(x Error: Quartus II Analysis Synthesis was unsuccessful. 3 errors. 0 warnings 图5-9全程编译后出现报错信息 K的列

KX 康芯科技 图5-9 全程编译后出现报错信息 5.1.4 全程编译