HDLBits学习（PPT课件讲稿）CHAPTER 5 Sequential Circuits（Latches & Flip-Flops）

CHAPTER 5 Sequential Circuits Latches Flip-Flops

CHAPTER 5: Sequential Circuits: Latches & Flip-Flops

Sequential circuit a There are two types of sequential circuits Synchronous(latch mode) sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock Asynchronous(fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time(clockless)

Sequential Circuit ◼ There are two types of sequential circuits: ➢ Synchronous (latch mode) sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. ➢ Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless)

Sequential circuit Models SYSTEM SYSTEM S OUTPUT VARIABLES VARIABLES COMBINATIONAL LOGIC STATE Mo EXCITATION VARIABLES VARIABlES AEMORY X

Sequential Circuit Models

Sequential circuit Models Falling or Negative Clock E CLOCK t+1 t+2 t+3 t+4

Sequential Circuit Models

Sequential circuit Models Excitation variables INPUT(t)斗 Combinational Combinational Memory ranson ogIc (f) g OUTPUT(O) State Variables

Sequential Circuit Models Excitation Variables Memory M State Variables CLK (E) Combinational Transform (f) INPUT(t) （S） Combinational Logic （g） OUTPUT(O)

Several subsets of the general sequential circuit model ExcitationⅤ ariables INPUT(t)- Combinational Combinational Memory Transform M (S) (g) OUTPUT(O) State Variables E=f Excitation variables S,+1=f(S,E INPUT(t)→ Combin Combinational O=gs Memory Transform M (S) OUTPUT(O) State variables sequential delay model

Several Subsets of the general sequential circuit model Excitation Variables Memory M State Variables CLK (E) Combinational Transform (f) INPUT(t) （S） Combinational Logic （g） OUTPUT(O) Excitation Variables Memory M State Variables CLK (E) Combinational Transform (f) INPUT(t) （S） Combinational Logic （g） OUTPUT(O) sequential delay model E=f(I) St+1=f(St ,E) O=g(St )

Several subsets of the general sequential circuit model Excitation Variables INPUT(t) Combinational Combinational Memory Transform CLK (S) OUTPUT(O) State variables Simple sequential counter model E=f(St S+1=f(S,E) O=gsy

Several Subsets of the general sequential circuit model Excitation Variables Memory M State Variables CLK (E) Combinational Transform (f) INPUT(t) （S） Combinational Logic （g） OUTPUT(O) Simple sequential counter model E=f(St ) St+1=f(St ,E) O=g(St )

Several subsets of the general sequential circuit model Excitation Variables E=f(I INPUT(t)- Combinational H(E) Memory Combinational OUTPUT(O) f(s,E Moore sequential circuit model Excitation Variables E=f(,Sy INPUT(t) Combinational Memory Combinational OUTPUT(O) State Variables Mealy sequential circuit model

Several Subsets of the general sequential circuit model Excitation Variables Memory M State Variables CLK (E) Combinational Transform (f) INPUT(t) （S） Combinational Logic （g） OUTPUT(O) Excitation Variables Memory M State Variables CLK (E) Combinational Transform (f) INPUT(t) （S） Combinational Logic （g） OUTPUT(O) Moore sequential circuit model Mealy sequential circuit model E=f(I,St ) St+1=f(St ,E) O=g(St ) E=f(I,St ) St+1=f(St ,E) O=g(I,St )

Alternatives in ff choice Type of FF d Q SR 八 CLK CLK positive gative JK edge-triggered edge-triggered flip-flop flip-flop T Type of triggering Untriggered(asynchronous) Level-triggered(C=1) CLK Edge-triggered(rising or falling edge transparent ofc (level-sensitive) latch

Alternatives in FF choice ◼ Type of FF ➢ SR ➢ D ➢ JK ➢ T ◼ Type of triggering ➢ Untriggered (asynchronous) ➢ Level-triggered (C=1) ➢ Edge-triggered (rising or falling edge of C) D Q CLK positive edge-triggered flip-flop D Q G CLK transparent (level-sensitive) latch D Q CLK negative edge-triggered flip-flop

Clock Signal Clock generator: periodic train of clock pulses Figure 5.1 Clock signals T

Clock Signal Clock generator: Periodic train of clock pulses