《ARM技术及其应用》课程教学资源（文献资料）arm201904

Review-ILBTheAArch64ALAAArch64ALProgrammers'ModelAArch64ALMemoryModelARMO42019-3-14

Review – II B The AArch64 ALA  AArch64 AL Programmers’ Model  AArch64 AL Memory Model ARM04 2019-3-14 1

IlARMArchitectureA ArchitectureIntroductionBTheAArch64ALA CThe AArch64InstructionSet D The AArch64 SLAETheAArch32ALA FTheAArch32InstructionSetsGTheAArch32SLAHExternal DebugIMemory-mappedComponentsJAppendixesARM042019-3-14

II ARM Architecture ARM04 2019-3-14 2  A Architecture Introduction  B The AArch64 ALA  C The AArch64 Instruction Set  D The AArch64 SLA  E The AArch32 ALA  F The AArch32 Instruction Sets  G The AArch32 SLA  H External Debug  I Memory-mapped Components  J Appendixes

CTheAArch64JSC1 A64ISIntroduction福C2A641SDescriptionC3.A64ISOverviewC4A64ISEncodingC5A64SystemlnstructionsC6A64BaseInstructions图C7SIMD&FPInstructions图口C8SummaryARM042019-3-14

C The AArch64 IS ARM04 2019-3-14 3  C1 A64 IS Introduction  C2 A64 IS Description  C3 A64 IS Overview  C4 A64 IS Encoding  C5 A64 System Instructions  C6 A64 Base Instructions  C7 SIMD & FP Instructions  C8 Summary

C1 A64JSIntroduction C1.1 A64 introductionC1.2Assemblerlanguage C1.3 Address generation C1.4 Instruction aliasesARM042019-3-14

C1 A64 IS Introduction ARM04 2019-3-14 4  C1.1 A64 introduction  C1.2 Assembler language  C1.3 Address generation  C1.4 Instruction aliases

Cl.1A64introduction A64 is the instruction set of AArch64A64instructionshaveawidthof 32bitsA64has a regularbit encoding structureA64encodingsbreakdownintogroups All encodings that are not fully defined are described as unallocatedand executing an unallocatedinstructionresults in an UndefinedInstructionexceptionARMO42019-3-14

C1.1 A64 introduction ARM04 2019-3-14 5  A64 is the instruction set of AArch64  A64 instructions have a width of 32 bits  A64 has a regular bit encoding structure  A64 encodings break down into groups  All encodings that are not fully defined are described as unallocated, and executing an unallocated instruction results in an Undefined Instruction exception

NotpresentcomparedtoA32 Conditionalexecution operationsA64 doesnotincludetheconceptof predicatedorconditionalexecutionBenchmarkingshowsthatmodernbranchpredictorsworkwell enoughthatpredicated execution of instructions does not offer sufficientbenefit to justifyitssignificantuseof opcode space,and itsimplementation costin advancedimplementations Load Multiple is replaced by load/store pairCoprocessorinstructionsisreplacedbysysteminstructionsARM042019-3-14

Not present compared to A32 ARM04 2019-3-14 6  Conditional execution operations  A64 does not include the concept of predicated or conditional execution  Benchmarking shows that modern branch predictors work well enough that predicated execution of instructions does not offer sufficient benefit to justify its significant use of opcode space, and its implementation cost in advanced implementations  Load Multiple is replaced by load/store pair  Coprocessor instructions is replaced by system instructions

C1.2Assemblerlanguage C1.2.1 Common syntax terms C1.2.2Instruction Mnemonics C1.2.3 Condition Codes C1.2.4 Register namesARM042019-3-14

C1.2 Assembler language ARM04 2019-3-14 7  C1.2.1 Common syntax terms  C1.2.2 Instruction Mnemonics  C1.2.3 Condition Codes  C1.2.4 Register names

C1.2.1 CommonsyntaxtermsUpper & Lower口<>, 0,[], a/b ±,#,uimmn,simmn口 //Single spacesARM042019-3-14

C1.2.1 Common syntax terms ARM04 2019-3-14 8  Upper & Lower  <>, {}, [ ], a|b  ±, #, uimmn, simmn  //  Single spaces

Upper&Lower Instruction mnemonics and register names are both upper- and lowercase, but not mixed caseProgramanddatalabelsarecase-sensitive Upper-caseis fixed and lower-case is variableXn indicates that the X is required, followed by a variable register number,suchasX29ARMO42019-3-14

Upper & Lower ARM04 2019-3-14 9  Instruction mnemonics and register names are both upper- and lower￾case, but not mixed case  Program and data labels are case-sensitive  Upper-case is fixed and lower-case is variable  Xn indicates that the X is required, followed by a variable register number, such as X29

10 Any text enclosed by angle braces, , is a value that the usersuppliesARM042019-3-14

ARM04 2019-3-14 10  Any text enclosed by angle braces, , is a value that the user supplies