《ARM技术及其应用》课程教学资源（文献资料）arm201903

Review-IlA ArchitectureIntroductionArchitectureverviewArchitectureprofilesArchitecturalconcepts Data typesFP&SIMDCrypto Extension Memory modelARM032019/3/3

Review – II A Architecture Introduction  Architecture verview  Architecture profiles  Architectural concepts  Data types  FP & SIMD  Crypto Extension  Memory model ARM03 2019/3/3 1

IlARMArchitectureA Architecture IntroductionBTheAArch64ALACTheAArch64ISDTheAArch64SLAETheAArch32ALAFTheAArch32ISGTheAArch32SLAHExternal DebugIMemory-mapped ComponentsJAppendixesARM032019/3/3

II ARM Architecture ARM03 2019/3/3 2  A Architecture Introduction  B The AArch64 ALA  C The AArch64 IS  D The AArch64 SLA  E The AArch32 ALA  F The AArch32 IS  G The AArch32 SLA  H External Debug  I Memory-mapped Components  J Appendixes

ILBTheAArch64ALAB1AArch64ALProgrammersModel国B2AArch64ALMemoryModel口B3SummaryARM032019/3/3

II B The AArch64 ALA ARM03 2019/3/3 3  B1 AArch64 AL Programmers’ Model  B2 AArch64 AL Memory Model  B3 Summary

B1AArch64ALProgrammersModel B1.1 Exceptions in AArch64B1.2Registers inAArch64 B1.3 Software control at ELOB1.4SummaryARM032019/3/3

B1 AArch64 AL Programmers’ Model ARM03 2019/3/3 4  B1.1 Exceptions in AArch64  B1.2 Registers in AArch64  B1.3 Software control at EL0  B1.4 Summary

iB1.1ExceptionsinAArch64Exception is the changeof programflow7 Exception levels (ELO-EL3)show execution privilege ELO is the lowest-level unprivileged execution EL1, EL2 and EL3 are higher privileged executionOSrunsatbothEL1andELO Application runs at ELOARM032019/3/3

B1.1 Exceptions in AArch64 ARM03 2019/3/3 5  Exception is the change of program flow  Exception levels (EL0-EL3) show execution privilege  EL0 is the lowest-level unprivileged execution  EL1, EL2 and EL3 are higher privileged execution  OS runs at both EL1 and EL0  Application runs at EL0

B1.2RegistersinAArch64 B1.2.1 Registers in AArch64B1.2.2Process stateB1.2.3System registersARM032019/3/3

B1.2 Registers in AArch64 ARM03 2019/3/3 6  B1.2.1 Registers in AArch64  B1.2.2 Process state  B1.2.3 System registers

B1.2.1RegistersinAArch64RO-R3O SP PC口 VO-V31口 FPCR,FPSR口 ZRARM032019/3/3

B1.2.1 Registers in AArch64 ARM03 2019/3/3 7  R0-R30  SP  PC  V0-V31  FPCR, FPSR  ZR

RO-R3O□31GPRs Each registercan be accessed as64-bit GPR named X0 toX3032-bitGPRnamedWOtoW306332|310RnkWnXnFigureB1-1General-purposeregisternamingARMO32019/3/3

R0-R30 ARM03 2019/3/3 8  31 GPRs  Each register can be accessed as  64-bit GPR named X0 to X30  32-bit GPR named W0 to W30

RO-R7Call parameter and return result registersARM032019/3/3

R0-R7 ARM03 2019/3/3 9  Call parameter and return result registers

R810 Indirect call result location registerARM032019/3/3

R8 ARM03 2019/3/3 10  Indirect call result location register