《ARM技术及其应用》课程教学资源（文献资料）arm201905

Review-IlCTheAArch64InstructionSetA64 IS IntroductionA64ISDescriptionsA64IS OverviewA64 IS EncodingA64SystemlnstructionsA64BaseInstructionsSIMD&FPInstructionsARM052019-3-17

Review – II C The AArch64 Instruction Set  A64 IS Introduction  A64 IS Descriptions  A64 IS Overview  A64 IS Encoding  A64 System Instructions  A64 Base Instructions  SIMD & FP Instructions ARM05 2019-3-17 1

IlARMArchitecture AArchitecture IntroductionBTheAArch64ALA CTheAArch64InstructionSet D The AArch64 SLAETheAArch32ALA FTheAArch32InstructionSetsGTheAArch32SLAHExternal DebugIMemory-mappedComponentsJAppendixesARM052019-3-17

II ARM Architecture ARM05 2019-3-17 2  A Architecture Introduction  B The AArch64 ALA  C The AArch64 Instruction Set  D The AArch64 SLA  E The AArch32 ALA  F The AArch32 Instruction Sets  G The AArch32 SLA  H External Debug  I Memory-mapped Components  J Appendixes

DTheAArch64SLAD1 A64SLProgrammers'Model口D2A64 Self-hosted Debug口D3A64SLMemoryMode!D4A64VMSA7D5Performance MonitorsD6A64GenericTimerD7A64SystemRegisterD8SummaryARM052019-3-17

D The AArch64 SLA ARM05 2019-3-17 3  D1 A64 SL Programmers’ Model  D2 A64 Self-hosted Debug  D3 A64 SL Memory Model  D4 A64 VMSA  D5 Performance Monitors  D6 A64 Generic Timer  D7 A64 System Register  D8 Summary

D1A64SLProgrammersModel D1.1ExceptionlevelsD1.2ExceptiontermsD1.3Execution states D1.4 Security statesD1.5 VirtualizationD1.6 SL RegistersD1.7ProcessstateD1.8PC&SPalignmentD1.9ResetD1.10ExceptionentryARM052019-3-17

D1 A64 SL Programmers’ Model ARM05 2019-3-17 4  D1.1 Exception levels  D1.2 Exception terms  D1.3 Execution states  D1.4 Security states  D1.5 Virtualization  D1.6 SL Registers  D1.7 Process state  D1.8 PC&SP alignment  D1.9 Reset  D1.10 Exception entry

D1A64SLProgrammers'ModelD1.11ExceptionreturnD1.12ExceptionhierarchyD1.13Syncexception D1.14 Async exception口D1.15ControlsathigherELs口D1.16 System calls口D1.17 Low-power state口D1.18 Self-hosted debug口D1.19 Performance Monitors口D1.20 Interprocessing口 D1.21 ConfigurationsARM052019-3-17

D1 A64 SL Programmers’ Model ARM05 2019-3-17 5  D1.11 Exception return  D1.12 Exception hierarchy  D1.13 Sync exception  D1.14 Async exception  D1.15 Controls at higher ELs  D1.16 System calls  D1.17 Low-power state  D1.18 Self-hosted debug  D1.19 Performance Monitors  D1.20 Interprocessing  D1.21 Configurations

D1.1 Exception levelsARM052019-3-17

D1.1 Exception levels ARM05 2019-3-17 6

AArch32->AArch64transitionTrustedApp2TrustedApp1App1App2App2ELOApp1++++-+++GuestOperatingSystem1GuestOperatingSystem2SecureWorld OsEL1AArch64->AArch32transitionAArch64:separateprivilege levelsVirtualMachineMonitor(VMM)orAArch32:EL2same privilege levelHypervisor+.+++++++++++++++++++++++++++++++++++++++++++++++EL3(TrustZone)MonitorExceptionLevelArchitectureELO forunprivileged application executionEL1 for privileged OS executionEL2forhypervisor,virtualizationof Non-secure stateEL3 for secure monitor,which switches between Secure and Non-secure stateEL1-EL3(exceptforELO)havetheirown translation regime & controlregistersARM052019-3-17

7 ARM05 2019-3-17 Exception Level Architecture EL0 for unprivileged application execution EL1 for privileged OS execution EL2 for hypervisor, virtualization of Non-secure state EL3 for secure monitor, which switches between Secure and Non-secure state EL1-EL3 (except for EL0) have their own translation regime & control registers

AArch32->AArch64transitionTrustedApp2TrustedApp1App1App2App1App2ELOGuestOperatingSystem1GuestOperatingSystem2SecureWorld OsEL1AArch64->AArch32transitionAArch64:separateprivilegelevelsVirtualMachineMonitor(VMM)orAArch32:EL2same privilege levelHypervisor++++++++++++++++++++++++++.+++++++++++++++.EL3(TrustZone)MonitorExecutionLevel TransitionOn taking exception:Exceptionlevel increase or remainIt is called the target Exception levelELo can'tbe an target Exception levelOn returning from exception:Exception level decrease or remainARM052019-3-17

8 ARM05 2019-3-17 Execution Level Transition On taking exception: Exception level increase or remain It is called the target Exception level EL0 can’t be an target Exception level On returning from exception: Exception level decrease or remain

AArch32->AArch64transitionTrustedApp2TrustedApp1App1App2App2ELOApp1GuestOperatingSystem1GuestOperatingSystem2SecureWorld OsEL1AArch64->AArch32transitionAArch64:separateprivilege levelsVirtualMachineMonitor(VMM)orAArch32:EL2sameprivilege leveHypervisor++++++++++++++++++++++++++++++++++++++++++.EL3(TrustZone)MonitorExceptionlevelResourcesResources for current Exception level and current Security stateResources for low Exception levels and current Security stateFor example,PE at EL3 can access all resources at all Exceptionlevels,forbothSecuritystatesARM052019-3-17

9 ARM05 2019-3-17 Exception level Resources Resources for current Exception level and current Security state Resources for low Exception levels and current Security state For example, PE at EL3 can access all resources at all Exception levels, for both Security states

D1.2Exceptionterms10D1.2.1Precise&lmprecise exceptions D1.2.2 Sync&Async exceptionsARM052019-3-17

D1.2 Exception terms ARM05 2019-3-17 10  D1.2.1 Precise&Imprecise exceptions  D1.2.2 Sync&Async exceptions