《ARM技术及其应用》课程教学资源（文献资料）arm201908

Review-Exynos4412SoCA1OVERVIEW口 2 PIN MAP3MEMORYMAP□ 4 CHIP ID口5BOOTING口6 GPIO□ 7 CMU口8 PMUARM082019-4-7

Review – Exynos4412 SoC A ARM08 2019-4-7 1  1 OVERVIEW  2 PIN MAP  3 MEMORY MAP  4 CHIP ID  5 BOOTING  6 GPIO  7 CMU  8 PMU

IIExynos4412SoCB9INTERRUPT1口10INTERRUPT2口11DMAC12REGISTERS□13CORESIGHT14TZPC15TZASC16MMU1口17MMU2口18DMCARM082019-4-7

III Exynos4412 SoC B ARM08 2019-4-7 2  9 INTERRUPT1  10 INTERRUPT2  11 DMAC  12 REGISTERS  13 CORESIGHT  14 TZPC  15 TZASC  16 MMU1  17 MMU2  18 DMC

IIExynos4412SoCB19SROM20FLASH□21 EBI口22SD/MMC□23MS 24 TIMER25 MCT口26 WD口27 RTC口ARM082019-4-7

III Exynos4412 SoC B ARM08 2019-4-7 3  19 SROM  20 FLASH  21 EBI  22 SD/MMC  23 MS  24 TIMER  25 MCT  26 WD  27 RTC

9INTERRUPTT9INTERRUPTCONTROLLER

9 INTERRUPT 1 9 INTERRUPT CONTROLLER

9INTERRUPT1 9.1 Overview 9.2 Interrupt Sources9.3Functional Description 9.4 Handling and Prioritizing9.5RegisterDescription 9.6 SummaryARM082019-4-7

9 INTERRUPT 1  9.1 Overview  9.2 Interrupt Sources  9.3 Functional Description  9.4 Handling and Prioritizing  9.5 Register Description  9.6 Summary ARM08 2019-4-7 5

9.1Overview GlC(Generic InterruptController)manages: interrupt register configurating interrupt enabling,disabling,and generating interrupt masking and prioritizing software interrupt generatingARMsecurityextensionsARM082019-4-7

9.1 Overview  GIC (Generic Interrupt Controller) manages:  interrupt register configurating  interrupt enabling, disabling, and generating  interrupt masking and prioritizing  software interrupt generating  ARM security extensions ARM08 2019-4-7 6

9.1 Overview 9.1.1 Features 9.1.2 Security 9.1.3 Configuration 9.1.4 TerminologiesARM082019-4-7

9.1 Overview  9.1.1 Features  9.1.2 Security  9.1.3 Configuration  9.1.4 Terminologies ARM08 2019-4-7 7

9.1.1FeaturesThree interrupt typesSGl(SoftwareGenerated Interrupt)PPI (PrivatePeripheral Interrupt)SPI(SharedPeripheral Interrupt)ProgrammableinterruptsInterruptenabling or disablingProcessorsthat receiveinterruptInterrupt priority levelInterrupt Security stateARM082019-4-7

9.1.1 Features  Three interrupt types  SGI (Software Generated Interrupt)  PPI (Private Peripheral Interrupt)  SPI (Shared Peripheral Interrupt)  Programmable interrupts  Interrupt enabling or disabling  Processors that receive interrupt  Interrupt priority level  Interrupt Security state ARM08 2019-4-7 8

9.1.2Security Configuring secure & nonsecure interruptsSecure accesses RW secure &nonsecure interruptsNonsecure accesses only RW nonsecure interrupts Signaling secure &nonsecureinterruptrequestsSecure interrupt signals IRQorFIQ interruptrequestNonsecure interrupt signals IRQinterrupt requestPrioritizingsecure&nonsecureinterrupts Locking configuration of secure interruptsARMO82019-4-7

9.1.2 Security  Configuring secure & nonsecure interrupts  Secure accesses RW secure & nonsecure interrupts  Nonsecure accesses only RW nonsecure interrupts  Signaling secure & nonsecure interrupt requests  Secure interrupt signals IRQ or FIQ interrupt request  Nonsecure interrupt signals IRQ interrupt request  Prioritizing secure & nonsecure interrupts  Locking configuration of secure interrupts ARM08 2019-4-7 9

9.1.3Configuration10The features depend on configuration are:Exynos4412SCPGICConfiguration160interruptsincludingSGls,PPlsandSPls32×4=128SPlinterruptrequests Table 9-1 describes GlC configuration valuesARM082019-4-7

9.1.3 Configuration  The features depend on configuration are:  Exynos 4412 SCP GIC Configuration  160 interrupts including SGIs, PPIs and SPIs  32×4 = 128 SPI interrupt requests  Table 9-1 describes GIC configuration values ARM08 2019-4-7 10