广东海洋大学：《VHDL程序设计语言》课程教学资源（实验指导）实验五 Clocks and Timers

Laboratory Exercise 5 Clocks and Timers This is an exercise in implementing and using a real-time clock. PartI Implement a 3-digit BCD counter.Display the contents of the counter on the 7-segment displays,HEX2-0.Derive a control signal,from the 50-MHz clock signal provided on the Altera DE2 board,to increment the contents of the counter at one-second intervals.Use the pushbutton switch KEYo to reset the counter to 0. 1.Create a new Quartus II project which will be used to implement the desired circuit on the DE2 board. 2.Write a VHDL file that specifies the desired circuit. 3.Include the VHDL file in your project and compile the circuit. 4.Simulate the designed circuit to verify its functionality 5.Assign the pins on the FPGA to connect to the 7-segment displays and the pushbutton switch,as indicated in the User Manual for the DE2 board. 6.Recompile the circuit and download it into the FPGA chip. 7.Verify that your circuit works correctly by observing the display. Part II Design and implement a circuit on the DE2 board that acts as a time-of-day clock.It should display the hour(from 0 to 23)on the 7-segment displays HEX7-6,the minute (from 0 to 60)on HEX5-4 and the second (from 0 to 60) on HEX3-2.Use the switches SW15-0 to preset the hour and minute parts of the time displayed by the clock. Part III Design and implement on the DE2 board a reaction-timer circuit.The circuit is to operate as follows: 1.The circuit is reset by pressing the pushbutton switch KEYo. 2.After an elapsed time,the red light labeled LEDRo turns on and a four-digit BCD counter starts counting in intervals of milliseconds.The amount of time in seconds from when the circuit is reset until LEDRo is turned on is set by switches SW7-0. 3.A person whose reflexes are being tested must press the pushbutton KEY3 as quickly as possible to turn the LED off and freeze the counter in its present state.The count which shows the reaction time will be displayed on the 7-segment displays HEX2-0. Copyright C2006 Altera Corporation. 1

Laboratory Exercise 5 Clocks and Timers This is an exercise in implementing and using a real-time clock. Part I Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2−0. Derive a control signal, from the 50-MHz clock signal provided on the Altera DE2 board, to increment the contents of the counter at one-second intervals. Use the pushbutton switch KEY 0 to reset the counter to 0. 1. Create a new Quartus II project which will be used to implement the desired circuit on the DE2 board. 2. Write a VHDL file that specifies the desired circuit. 3. Include the VHDL file in your project and compile the circuit. 4. Simulate the designed circuit to verify its functionality. 5. Assign the pins on the FPGA to connect to the 7-segment displays and the pushbutton switch, as indicated in the User Manual for the DE2 board. 6. Recompile the circuit and download it into the FPGA chip. 7. Verify that your circuit works correctly by observing the display. Part II Design and implement a circuit on the DE2 board that acts as a time-of-day clock. It should display the hour (from 0 to 23) on the 7-segment displays HEX7−6, the minute (from 0 to 60) on HEX5−4 and the second (from 0 to 60) on HEX3−2. Use the switches SW15−0 to preset the hour and minute parts of the time displayed by the clock. Part III Design and implement on the DE2 board a reaction-timer circuit. The circuit is to operate as follows: 1. The circuit is reset by pressing the pushbutton switch KEY0. 2. After an elapsed time, the red light labeled LEDR0 turns on and a four-digit BCD counter starts counting in intervals of milliseconds. The amount of time in seconds from when the circuit is reset until LEDR 0 is turned on is set by switches SW7−0. 3. A person whose reflexes are being tested must press the pushbutton KEY 3 as quickly as possible to turn the LED off and freeze the counter in its present state. The count which shows the reaction time will be displayed on the 7-segment displays HEX2-0. Copyright
c 2006 Altera Corporation. 1