《电路》（英文版）17-6 Writing a set of normal form equations

817-6 Writing a set of normal form equations 1. Establish a normal tree tree branches -,, C(oa,R cot ree(chords)-io,l(ia, r) 2. Assign voltage and current variables. Assign a voltage (with polarity reference) to every capacitor and a current(with arrow) to every inductor; there are the state variables Indicate the voltage across every tree branch and the current through every link in terms of the source voltages, source currents, and the state variables, if possible; otherwise assign a new voltage or current variable to that resistive tree branch or link

§17-6 Writing a set of normal form equations 1. Establish a normal tree.    − − − cot ( ) , ( , ) , ( , ) ree chords i L i R tree branches C R s d  s d 2. Assign voltage and current variables. Assign a voltage (with polarity reference) to every capacitor and a current (with arrow) to every inductor; there are the state variables.Indicate the voltage across every tree branch and the current through every link in terms of the source voltages, source currents,and the state variables, if possible; otherwise, assign a new voltage or current variable to that resistive tree branch or link

3. Write the C equations( kcl)--fundamental cutset 4. Write the L equations (Kvl)--fundamental loop 5. Write the r equations(if necessary). 6. Write the normal form equations. Substitute the expressions for each UR and ir into the equations obtained in steps 3 and 4, thus eliminating all resistor variables

3. Write the C equations(KCL)--fundamental cutset. 4. Write the L equations(KVL)--fundamental loop. 5. Write the R equations(if necessary). 6. Write the normal form equations. Substitute the expressions for each into the equations obtained in steps 3 and 4, thus eliminating all resistor variables. R R  and i

The network contains a loop in which every element is a capacitor or voltage source. the other occurs if there in a node or supernode that is connected to the remainder of the circuit only by inductors and current sources When either of these events occurs, we meet the challenge by leaving a capacitor out of the tree in one case and omitting an inductor from the cotree in the other. Example Solution: 0.3H n=a.,+3e) 0.3i,-1.8te dt )r2u() U42=4(1+3e)=41+12e12 (+32)∴0.1+0.31-1:8e-+4i1+12e--2r2u(t)=0 3e 2tu(tk Or (4.5t-30)+5tu(t)

The network contains a loop in which every element is a capacitor or voltage source, the other occurs if there in a node or supernode that is connected to the remainder of the circuit only by inductors and current sources. When either of these events occurs, we meet the challenge by leaving a capacitor out of the tree in one case and omitting an inductor from the cotree in the other. 2 2 0.3 1.8 ( 3 ) 0.3 ' 1 1 0.3 t t H i t e dt d i e − − = − +  = 2 2 4 4( 1 3 ) 4 1 12 t t i e i e − −   = + = + 10 (4.5 30) 5 ( ) 2 1 ' 1 2 or i i e t t u t t = − + − + − Solution: 0.1 0.3 1.8 4 12 2 ( ) 0 2 1 ' 1 ' 1 2 2  + − + + − = − − i i t e i e t u t t t 1 i 2 3 t e − ( 3 ) 2 1 t i e − + − + 2 ( ) 2 t u t − + 0.1H 2t u(t)V 2 e A t 2 3 − 0.3H 4 Example: