VHDL：Examples of Finite State Machines（FSMs）Counters and pattern generators

Chapter 6 Examples of finite State machines (FSMS) Counters and pattern generators VHDL 6. examples of FSM ver. 8a

Chapter 6 Examples of Finite State Machines (FSMs) Counters and pattern generators VHDL 6. examples of FSM ver.8a 1

Counters and pattern generators Up/down counters: generate a sequence of gradually increasing or decreasing counting patterns according to the clock and inputs (E.g. digital clock, 1, 2, 3, 4 Pattern generators: generate any patterns of finite states. Use state diagrams to design. ( E.g traffic light, red, green, yellow. VHDL 6. examples of FSM ver. 8a

Counters and pattern generators • Up/down counters: generate a sequence of gradually increasing or decreasing counting patterns according to the clock and inputs. (E.g. digital clock, 1,2,3,4..) • Pattern generators: generate any patterns of finite states. Use state diagrams to design. (E.g. traffic light,red,green, yellow..) VHDL 6. examples of FSM ver.8a 2

Up/down counters are FSms Asyn. clock -more delay among outputs, less logic the output of one state register is the clock of another state register Syn clock -less delay among outputs more logic all clock inputs of state registers (flip-lops are connected Examples here are all Moore machines (output depends on state registers. VHDL 6. examples of FSM ver. 8a

Up/down counters are FSMs • Asyn.clock -more delay among outputs, less logic – the output of one state register is the clock of another state register. • Syn. clock -less delay among outputs, more logic – all clock inputs of state registers (flip-lops) are connected. • Examples here are all Moore machines (output depends on state registers.) VHDL 6. examples of FSM ver.8a 3

Two design methods Asynchronous clock design Easier to design More delay at outputs Synchronous clock design More complex Less time delay at outputs VHDL 6. examples of FSM ver. 8a

Two design methods • Asynchronous clock design – Easier to design – More delay at outputs • Synchronous clock design – More complex – Less time delay at outputs VHDL 6. examples of FSM ver.8a 4

4-bit asynchronous clock down counter(Moore) CLK in STD logic: RESET in STD logiC: CoUNTO, CoUNT1, CoUNT2, COUNT3: inout STD LOGIC; architecture Behavioral of asyn_counter is_ Asynchronous clocks process(reset, clk, counfo, count1, count2)begin if reset= 1' then Each line is countO<=0 count1<=0 an Flip-Flop count2<0 count3<=0 else if(rising_edge(clk ))then counto not counto end if if(rising_edge(counto))then count1 < not count1 ena if(rising_edge(count1 ))then count2< not count2 end if eage( coun nt2)then count3<= not count3 if nd if. end process A 4-BIT DOWN COUNTER end behavioral VHDL 6. examples of FSM ver. 8a

4-bit Asynchronous clock down counter (Moore) CLK: in STD_LOGIC; RESET: in STD_LOGIC; COUNT0, COUNT1 , COUNT2 , COUNT3 : inout STD_LOGIC; VHDL 6. examples of FSM ver.8a 5 Each line is an Flip-Flop Asynchronous clocks A 4-bit down counter

library IEEE; -(vivado 2014 34 ok) use IEEE std logic_1164.all; entity asyn_ counter is port( clk: in std logic reset: in std logic counto, count1, count2, count3: inout std logic); end asyn counter; architecture Behavioral of asyn counter is process(reset, clk, counto, count1, count2 )begin if reset =1 then counto<=0: count1<=0 count2<=0; count3<= 0 else if(rising_edge(clk) then counto < not counto; d if if(rising_edge(counto)) then count1 < not count 1 nd if; if(rising_edge(count 1 )) then count2<= not count 2: end if: if(rising_edge count2 ) then count3<= not count3: end if: end if: end process; end behavioral: VHDL 6. examples of FSM ver. 8a

• library IEEE; --(vivado 2014.34 ok) • use IEEE.std_logic_1164.all; • entity asyn_counter is • port( clk: in std_logic; • reset: in std_logic; • count0,count1, count2, count3: inout std_logic); • end asyn_counter; • architecture Behavioral of asyn_counter is • begin • process(reset, clk, count0, count1, count2) begin • if reset ='1' then • count0<= '0'; count1<= '0'; • count2<= '0'; count3<= '0'; • else • if(rising_edge(clk)) then count0 <= not count0; • end if; • if(rising_edge(count0)) then count1 <= not count1; • end if; • if(rising_edge(count1)) then count2<= not count2; • end if; • if(rising_edge(count2)) then count3<= not count3; • end if; • end if; • end process; • end Behavioral; VHDL 6. examples of FSM ver.8a 6

Exercise on 6.1, 4-bit Asyn Student ID Clock Counter plot count and Name Date: check delay (Submit this at the end of the lecture Write the port declaration Plot Q(1),Q(2),Q 3 including delays Count(o) Count(1) Count(2) Count(3) D(2 D(3) FF 少FF 少FF PFF cloc k ck'to(0)ck" Q(ck" TQ(2)ck"TQ(3) δt= time delay at one ff reset k CIoc Q(0)-t Q(1) Q(2) VHDL 6. examples of FSM ver. 8a

Exercise on 6.1, 4-bit Asyn. Clock Counter. Plot count, and check delay • Write the port declaration. • Plot Q(1),Q(2),Q(3) including delays VHDL 6. examples of FSM ver.8a 7 FF FF FF FF clock Count(0) Count(1) Count(2) Count(3) reset clock Q(0) Q(1) Q(2) Q(3) t= time delay at one FF ck Q(0) ck Q(1)ck Q(2) ck Q(3) D(0) D(1) D(2) D(3) Student ID: __________________ Name: ______________________ Date:_______________ (Submit this at the end of the lecture.) t

Simulation result 5us 10us 15us 唱 threet ouro count1 品 count2 COunt3 VHDL 6. examples of FSM ver. 8a

Simulation result • VHDL 6. examples of FSM ver.8a 8

Synchronous clock counter design More difficult to design Less delay at outputs( more precise VHDL 6. examples of FSM ver. 8a

Synchronous clock counter design • More difficult to design • Less delay at outputs (more precise) VHDL 6. examples of FSM ver.8a 9

4-bit synchronous counter More complicated than asynchronous design fromhttp://web.cs.munca/paul/cs3724/material/web/notes/img191.png F Clock VHDL 6. examples of FSM ver. 8a

4-bit synchronous counter • More complicated than asynchronous design • from http://web.cs.mun.ca/~paul/cs3724/material/web/notes/img191.png VHDL 6. examples of FSM ver.8a 10