《嵌入式应用开发》课程教学资源（文献资料）AT24C02

Features.Low-voltageandStandard-voltageOperation,VcC=2.7V-5.5VInternallyOrganized128x8(1K),256x8(2K),512x8(4K),AMEL1024x8(8K),or2048x8(16K)·Two-wireSerialInterface:Schmitt Trigger,Filtered Inputsfor Noise SuppressionR:BidirectionalDataTransferProtocol·400kHzCompatibility8-byte Page(1K, 2K),16-bytePage (4K,8K, 16K)WriteModes·Partial PageWritesAllowedTwo-wire Serial.Self-timedWriteCycle(5msmax): High ReliabilityEndurance:OneMillionWriteCyclesEEPROMSmart-DataRetention:100Years-ESDProtection:>3000VCard Modules1K (128 x 8)DescriptionTheAT24C01A/02SC/04SC/08SC/16SCprovide1024/2048/4096/8192/16384bitsof2K (256 x 8)serial,electrically-erasable,andprogrammableread-onlymemory(EEPROM)orga-nizedas128/256/512/1024/2048wordsof8bitseach.Thedevicesareoptimizedfor4K (512 x 8)useinsmartcardapplicationswherelow-powerandlow-voltageoperationmaybeessential.ThedevicesareavailableinseveralstandardISO7816smartcardmodules8K (1024 x 8)(seeOrderingInformation,pages12-13).AlldevicesarefunctionallyequivalenttoAtmelserialEEPROMproductsofferedinstandardICpackages(PDIP,SOIC.TSSOP16K(2048x8)MAP),withtheexceptionoftheslaveaddressandwriteprotectfunctions,whicharenotrequiredforsmartcardapplications.AT24C01ASCTable1.PinConfigurationPad NameDescriptionISoModuleContactAT24C02SCVCCC1PowerSupplyVoltageAT24C04SCGNDGroundC5SCLC3Serial Clock InputAT24C08SCSDAC7Serial Data Input/OutputAT24C16SCNCNoConnectC2, C4, C6, C8Figure1.Card ModuleContactVCC = C1C5= GNDNC= C2C6= NCSCL= C3C7= SDANC = C4C8 = NC1610B-SEEPR-04/04IMEL

1 1610B–SEEPR–04/04 Features • Low-voltage and Standard-voltage Operation, VCC = 2.7V–5.5V • Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K), or 2048 x 8 (16K) • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 400 kHz Compatibility • 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes • Partial Page Writes Allowed • Self-timed Write Cycle (5 ms max) • High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3000V Description The AT24C01A/02SC/04SC/08SC/16SC provide 1024/2048/4096/8192/16384 bits of serial, electrically-erasable, and programmable read-only memory (EEPROM) orga￾nized as 128/256/512/1024/2048 words of 8 bits each. The devices are optimized for use in smart card applications where low-power and low-voltage operation may be essential. The devices are available in several standard ISO 7816 smart card modules (see Ordering Information, pages 12–13). All devices are functionally equivalent to Atmel serial EEPROM products offered in standard IC packages (PDIP, SOIC, TSSOP, MAP), with the exception of the slave address and write protect functions, which are not required for smart card applications. Table 1. Pin Configuration Figure 1. Card Module Contact Pad Name Description ISO Module Contact VCC Power Supply Voltage C1 GND Ground C5 SCL Serial Clock Input C3 SDA Serial Data Input/Output C7 NC No Connect C2, C4, C6, C8 NC VCC Two-wire Serial EEPROM Smart Card Modules 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) 16K (2048 x 8) AT24C01ASC AT24C02SC AT24C04SC AT24C08SC AT24C16SC

AMELAbsoluteMaximumRatings*NOTICE:Stressesbeyond those listed under"Absolute.55°Cto+125°COperatingTemperature..MaximumRatings"maycausepermanentdam-age to the device.This is a stress rating only and65°Cto+150°CStorage Temperaturefunctional operationof thedeviceatthese oranyVoltageonAnyPinotherconditions beyond thoseindicated inthe-1.0Vto+7.0VwithRespecttoGround.operationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumrating6.25VMaximumOperatingVoltageconditionsforextendedperiodsmayaffectdevicereliability..5.0mADCOutputCurrent.Figure2.BlockDiagramVCCGND,+STARTSCLSTOPSDALOGICSERIALENH.V.PUMP/TIMINGCONTROLLOGICLOADCOMPDATA RECOVERYDEVICEADDRESSCOMPARATORLOADINCR/WDATA WORDEEPROMADDR/COUNTERYDECSERIAL MUXDINDouT/ACKLOGICDouTPinDescriptionSERIALCLOCK(SCL):TheSCLinputisusedtopositiveedgeclockdataintoeachEEPROMdeviceandnegativeedgeclockdataoutofeachdeviceSERIALDATA(SDA):TheSDApin isbidirectional for serial datatransfer.Thispin isopen-draindrivenandmaybewire-ORedwithany numberofotheropen-drainoropen-collectordevices.Memory Organization AT24c01Asc,1K SERIAL EEPROM: Internally organized with 16pages of 8 byteseach,the1K requires a 7-bit data word address forrandom word addressingAT24C02SC,2KSERIALEEPROM:Internallyorganizedwith32pagesof8byteseach, the 2K requires an 8-bit data word address for random word addressing.AT24C01ASC/02SC/04SC/08SC/16SC21610B-SEEPR-04/04

2 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 Figure 2. Block Diagram Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open￾collector devices. Memory Organization AT24C01ASC, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing. AT24C02SC, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. Absolute Maximum Ratings Operating Temperature.−55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam￾age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature .−65°C to +150°C Voltage on Any Pin with Respect to Ground. −1.0V to +7.0V Maximum Operating Voltage . 6.25V DC Output Current. 5.0 mA

AT24C01ASC/02SC/04SC/08SC/16SCAT24C04SC,4KSERIALEEPROM:Internallyorganizedwith32pagesof16byteseach, the 4K requires a 9-bit data word address for random word addressing.AT24C08SC,8KSERIALEEPROM:Internallyorganizedwith64pagesof16byteseach,the8K requires a10-bit data wordaddress random wordaddressing.AT24C16SC,16KSERIALEEPROM:Internallyorganizedwith128pagesof16byteseach,the16krequiresan11-bitdatawordaddressrandomwordaddressing.PinCapacitanceTable 2. Pin Capacitance(1)Applicableoverrecommendedoperating rangefromTa=25C,f=1.0MHz,Vcc=+2.7VSymbolMaxUnitsTest ConditionConditionsCvo8pFVvo = OVInput/OutputCapacitance(SDA)CIN6pFViN= OVInput Capacitance (SCL)Note:1.Thisparameteris characterizedand isnot100%tested.DCCharacteristicsDC Characteristics(1)Table3.MinTypMaxSymbolParameterTest ConditionUnitsVVcc2.75.5Supply VoltageIcc0.4 1.0mASupplyCurrentVcc=5.0VREAD at 100kHz2.03.0lccmASupplyCurrent Vcc=5.0VWRITEat100kHz1.64.0μAIsB1Standby Current Vcc=2.7VViN=Vcc orGND8.018.0μAStandby Current Vcc = 5.0VVinN=Vcc OrGNDIsB2μA0.103.0IuInput Leakage CurrentViN=VccorGND3.0μAILoOutput Leakage Current0.05VouT=VccOrGNDInput Low Leve/(2)VILv0.6Vcc× 0.3Input High Level(2)ViHVVcc ×0.7Vcc + 0.5VoLV0.4Output Low Level Vcc = 3.0VloL= 2.1 mANotes:1.Applicableover recommended operating rangefrom:Tac=0°C to+70°C, Vcc=+2.7Vto+5.5V (unlessotherwise noted)2.Viminand Vimaxare reference only and are not tested.ACCharacteristicsTable 4. AC Characteristics(1)SymbolMinParameterMaxUnitsfscL400kHzClockFrequency,SCL1.2tLowUSClock Pulse Width Low0.6Clock Pulse Width HighustHIGHNoise Suppression Time(2)t50nsAA0.10.9ClockLowtoDataOut ValidusTimethebusmust befree beforeanew transmission can star(1)1.2tBUFusAIMEL31610B-SEEPR-04/04

3 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 AT24C04SC, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. AT24C08SC, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address random word addressing. AT24C16SC, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address random word addressing. Pin Capacitance Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics Notes: 1. Applicable over recommended operating range from: TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted) 2. VIL min and VIH max are reference only and are not tested. AC Characteristics Table 2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V Symbol Test Condition Max Units Conditions CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN Input Capacitance (SCL) 6 pF VIN = 0V Table 3. DC Characteristics(1) Symbol Parameter Test Condition Min Typ Max Units VCC Supply Voltage 2.7 5.5 V ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA ISB1 Standby Current VCC = 2.7V VIN = VCC or GND 1.6 4.0 µA ISB2 Standby Current VCC = 5.0V VIN = VCC or GND 8.0 18.0 µA ILI Input Leakage Current VIN = VCC or GND 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC or GND 0.05 3.0 µA VIL Input Low Level(2) −0.6 VCC x 0.3 V VIH Input High Level(2) VCC x 0.7 VCC + 0.5 V VOL Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V Table 4. AC Characteristics(1) Symbol Parameter Min Max Units fSCL Clock Frequency, SCL 400 kHz tLOW Clock Pulse Width Low 1.2 µs tHIGH Clock Pulse Width High 0.6 µs tI Noise Suppression Time(2) 50 ns tAA Clock Low to Data Out Valid 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start(1) 1.2 µs

AMELTable4.AC Characteristics(1) (Continued)SymbolParameterMinMaxUnits0.6Start Hold TimeustHD.STA0.6Start Setup TimesU.STAus0Data In Hold TimeμstHD.DATDataIn SetupTime100nstsu.DATInputs Rise Time(2)0.3tRμsInputs Fall Time(2)tF300ns0.6ustsu.STOStop Setup Time50nstoHData Out Hold Time5tWRWriteCycleTimemsEndurance(1)1M5.0V,25℃,Byte ModeWrite CyclesNote:ApplicableoverrecommendedoperatingrangefromTa=0°Cto+70C,Vcc=+2.7Vto+5.5V,CL=1TTLGateand100pFA.(unlessotherwisenoted)2. This parameter is characterized and is not 100% tested.DeviceOperationCLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-naldevice.DataontheSDApinmaychangeonlyduringSCL-lowtimeperiods(seeFigure3onpage5).Data changes duringSCL-highperiods will indicatea start or stopconditionasdefinedbelow.START CONDITION:A high-to-low transition of SDA with SCLhigh is a start conditionthat mustprecede any other command (seeFigure 4on page 6)STOP CONDITION:A low-to-high transition of SDA with SCLhigh is a stop condition.Afterareadsequence,theStopcommandwill placetheEEPROMinastandbypowermode(seeFigure4onpage6).ACKNOWLEDGE:All addressesanddatawords areseriallytransmittedtoandfromtheEEPROMin8-bitwords.Eachwordrequiresthereceivertoacknowledgethatithasreceivedavalidcommandordatabyte.DuringthetransmissionofcommandsfromthehosttotheEEPROM,theEEPROMwill sendazerotothehosttoacknowledgethat ithasreceivedayalidcommandbvte.Thisoccursontheninthclockcycleofthecommandbyte.Duringread operations,thehostwill sendazeroto theEEPROMtoacknowledgethat ithas receivedavaliddatabyteandthat it requeststhenext sequen-tialdatabytetobetransmitted duringthesubsequent eightclock cycles.Thisoccursonthe ninth clock cycle of the data byte. If the host does not transmit this acknowledge bit,theEEPROMwilldisablethereadoperationandreturntostandbymode.STANDBYMODE:TheAT24C01ASC/02SC/04SC/08SC/16SCfeaturealow-powerstandbymodethat isenableduponpower-upandafterthereceiptofthestopbitandthecompletionofanyinternaloperations.MEMORYRESET:Afteran interruption inprotocol,powerloss,orsystemreset,anytwo-wirepartcanberesetbyfollowingthesesteps:Clockupto9cycles.1.2. Look for SDA high in each cycle while SCL is high.3.Create a start condition as SDAis high.AT24C01ASC/02SC/04SC/08SC/16SC41610B-SEEPR04/04

4 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 Note: 1. Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 2. This parameter is characterized and is not 100% tested. Device Operation CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter￾nal device. Data on the SDA pin may change only during SCL-low time periods (see Figure 3 on page 5). Data changes during SCL-high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 4 on page 6). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 4 on page 6). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. Each word requires the receiver to acknowledge that it has received a valid command or data byte. During the transmission of commands from the host to the EEPROM, the EEPROM will send a zero to the host to acknowledge that it has received a valid command byte. This occurs on the ninth clock cycle of the com￾mand byte. During read operations, the host will send a zero to the EEPROM to acknowledge that it has received a valid data byte and that it requests the next sequen￾tial data byte to be transmitted during the subsequent eight clock cycles. This occurs on the ninth clock cycle of the data byte. If the host does not transmit this acknowledge bit, the EEPROM will disable the read operation and return to standby mode. STANDBY MODE: The AT24C01ASC/02SC/04SC/08SC/16SC feature a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss, or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition as SDA is high. tHD.STA Start Hold Time 0.6 µs tSU.STA Start Setup Time 0.6 µs tHD.DAT Data In Hold Time 0 µs tSU.DAT Data In Setup Time 100 ns tR Inputs Rise Time(2) 0.3 µs tF Inputs Fall Time(2) 300 ns tSU.STO Stop Setup Time 0.6 µs tDH Data Out Hold Time 50 ns tWR Write Cycle Time 5 ms Endurance(1) 5.0V, 25°C, Byte Mode 1M Write Cycles Table 4. AC Characteristics(1) (Continued) Symbol Parameter Min Max Units

LAT24C01ASC/02SC/04SC/08SC/16SCTiming DiagramsBus TimingFigure 1. Bus TimingLHIGHLOWtLOWSCLtsU.STAtHD.DATtHD.STAIsU.STOSDA INLASDAOUTNote:SCL:SerialClock,SDA:SerialDataI/OWrite Cycle TimingFigure2.WriteCycleTimingSCLSDA8th BIWORDn1A051STOPSTARTCONDITIONCONDITIONNotes:1.The write cycle timetwr is thetimefrom a valid stop conditionofa writesequence totheendoftheinternalclear/writecycle2.SCL:SerialClock,SDA:SerialDataI/OData ValidityFigure 3. Data ValiditySDASCLDATA STABLEDATA STABLEDATACHANGE351610B-SEEPR04/04

5 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 Timing Diagrams Bus Timing Figure 1. Bus Timing Note: SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing Figure 2. Write Cycle Timing Notes: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 2. SCL: Serial Clock, SDA: Serial Data I/O Data Validity Figure 3. Data Validity tWR(1) SDA SCL DATA STABLE DATA CHANGE DATA STABLE

AMELStart and Stop DefinitionFigure 4.Startand Stop DefinitionDACLSTARTSTOPOutputAcknowledgeFigure5.OutputAcknowledgeSCLDATA INDATAOUTSTARTACKNOWLEDGEAT24C01ASC/02SC/04SC/08SC/16SC61610B-SEEPR04/04

6 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 Start and Stop Definition Figure 4. Start and Stop Definition Output Acknowledge Figure 5. Output Acknowledge DA CL START STOP SCL DATA IN DATA OUT START ACKNOWLEDGE

LAT24C01ASC/02SC/04SC/08SC/16SCDeviceAddressingThe 1K,2K,4K,8K,and 16K EEPROM devices all require an 8-bit device address wordfollowing a start condition to enable the chip for a read or write operation (see Figure 6onpage7)The device address word consists of a mandatory"1","0","1","o"sequence for the firstfour most significant bits as shown.This is common to all the serial EEPROM devices.The nextthree bits ofthedevice address word arethemostsignificant data wordaddressbitsfortheAT24C16SC(16K)whichrequiresatotalof11addressbits.TheAT24C08SC(8K)requiresonly10totalwordaddressbits.Themostsignificanttwobitsare included in the device address word.The unused bit of thedevice addresswordshould be set to"0".The AT24C04SC (4K) requires only nine total data word addressbits.Themost significantbit is includedinthe deviceaddress word.Thetwounusedbitsof the device address word should be set to"0".The AT24Co2SC (2K) andAT24Co1ASC(1K)donotrequireanyaddressbitsinthedeviceaddressword.Thethree unused bits of thedevice address word should be set to"o".Theeighthbitofthedeviceaddress istheread/writeoperationselectbit.Areadopera-tion is initiated ifthis bitis high,anda writeoperation is initiated ifthis bitis low.Upon a compare of the deviceaddress,the EEPROM will output a"o"(ACK). If a suc-cessfulcompareisnotmade,thechipwillreturntoastandbystate(NOACK)Figure6.DeviceAddress01K/2KMSDLSBRWO4K8K0>00P1PORW16KUPURWNote:Po,P1,P2=Datawordaddressbits371610BSEEPR-04/04

7 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 Device Addressing The 1K, 2K, 4K, 8K, and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 6 on page 7). The device address word consists of a mandatory “1”, “0”, “1”, “0” sequence for the first four most significant bits as shown. This is common to all the serial EEPROM devices. The next three bits of the device address word are the most significant data word address bits for the AT24C16SC (16K), which requires a total of 11 address bits. The AT24C08SC (8K) requires only 10 total word address bits. The most significant two bits are included in the device address word. The unused bit of the device address word should be set to “0”. The AT24C04SC (4K) requires only nine total data word address bits. The most significant bit is included in the device address word. The two unused bits of the device address word should be set to “0”. The AT24C02SC (2K) and AT24C01ASC (1K) do not require any address bits in the device address word. The three unused bits of the device address word should be set to “0”. The eighth bit of the device address is the read/write operation select bit. A read opera￾tion is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0” (ACK). If a suc￾cessful compare is not made, the chip will return to a standby state (NO ACK). Figure 6. Device Address Note: P0, P1, P2 = Data word address bits 1K/2K 4K 8K 16K MSD LSB 1 0 1 0 0 0 0 R/W 1 0 1 0 0 0 P0 R/W 1 0 1 0 0 P1 P0 R/W 1 0 1 0 P2 P1 P0 R/W

AMELWriteOperationsBYTEWRiTE:Awriteoperationrequiresan8-bitdatawordaddressfollowingthedeviceaddresswordandacknowledgment.Uponreceiptofthisaddress,theEEPROMwillagainrespondwitha“o"(ACK)andthenclockinthefirst8-bitdataword.Followingreceiptofthe8-bitdataword,theEEPROMwilloutputa"o"(ACK)andtheaddressingdevice,suchasamicrocontroller,mustterminatethewriteseguencewithastopcondi-tion.At this time the EEPROM enters an internally-timed write cycle,twR,to thenonvolatilememory.All inputsaredisabledduringthiswritecycleandtheEEPROMwillnot respond until the write is complete (refer to Figure 7).Figure7.ByteWriteSTWRITESTOPARDEVICETDATAADDRESSWORDADDRESSSDA LINEMSBB2ARACKBWKPAGEWRITE:The 1K/2KEEPROM is capableof an 8-bytepagewrite,and the 4K, 8K,and16Kdevicesarecapableof16-bytepagewrites.Apagewriteisinitiatedthesameasabytewrite,butthemicrocontrollerdoesnotsenda stop condition after the first data word is clocked in.Instead, after the EEPROMacknowledgesreceiptofthefirstdataword,themicrocontrollercantransmitupto7(1K/2K)or15(4K,8K,16K)moredatawords.TheEEPROMwillrespondwitha"0"(ACK)after each data word received.The microcontroller mustterminate the page writesequencewithastopcondition(refertoFigure8).Figure 8.Page WriteSTARWRITLSTOPDEVICEETADDRESSDATA (n)DATA (n + 1)DATA (n + x)WORD ADDRESS(n)SDA LINEMSBBAACKACKACKOKBWKNote:*=DON'TCAREbitfor1KThedatawordaddresslowerthree(1K/2K)orfour(4K,8K,16K)bitsareinternallyincrementedfollowingthereceiptofeachdataword.Thehigherdatawordaddressbitsarenotincremented,retainingthememorypagerowlocation.Whenthewordaddress,internallygenerated,reachesthepageboundary,thefollowingbyteisplacedatthebeginningofthesamepage.Ifmorethaneight(1K/2K)or16(4K,8K,16K)datawordsaretransmittedtotheEEPROM,thedatawordaddresswill"rolloverandpreviousdatawillbeoverwritten.ACKNOWLEGEPOLLING:OncetheinternallytimedwritecyclehasstartedandtheEEPROM inputs are disabled,acknowledge polling can beinitiated.This involves send-inga startconditionfollowedbythedeviceaddressword.Theread/writebit isrepresentative of the operation desired.Only if the internal write cycle has completedAT24C01ASC/02SC/04SC/08SC/16SC81610B-SEEPR-04/04

8 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” (ACK) and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” (ACK) and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi￾tion. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 7). Figure 7. Byte Write PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K, and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 7 (1K/2K) or 15 (4K, 8K, 16K) more data words. The EEPROM will respond with a “0” (ACK) after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 8). Figure 8. Page Write Note: * = DON’T CARE bit for 1K The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or 16 (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send￾ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed W R I T E S T A R T WORD ADDRESS L S B DATA S T O P * (n) DATA (n) DATA (n + 1) DATA (n + x)

LAT24C01ASC/02SC/04SC/08SC/16SCwill the EEPROM respondwitha"o"(ACK),allowing theread orwrite sequencetocontinue.ReadOperationsReadoperationsareinitiatedthesamewayaswriteoperations,withtheexceptionthatthe read/write select bit in the deviceaddress word is setto"1",There are three readoperations:currentaddressread,randomaddressread,andsequential read.CURRENTADDRESSREAD:Theinternaldatawordaddresscountermaintainsthelastaddressaccessedduringthelastreadorwriteoperation,incrementedbyone.Thisaddressstaysvalidbetweenoperationsaslongasthechippowerismaintained.Theaddress "rollover"during read is from the last byte of the last memory page to the firstbyte of the first page.The address"rollover"during write is from the last byte of the cur-rentpagetothefirstbyteof thesamepage.Oncethe device addresswiththeread/write selectbit setto"1"is clocked inandacknowledgedbytheEEPROM,thecurrent addressdatawordisseriallyclockedout.The microcontroller does not respond with an input "o" but does generate a followingstopcondition(refertoFigure9)Figure9.CurrentAddressRead.STASTREOPARTDEVICEDADDRESSSDALINERADATAMLzosLcSBBWKACKRANDOMREAD:Arandomread requiresadummy"bytewritesequencetoload inthedatawordaddress.OncethedeviceaddresswordanddatawordaddressareclockedinandacknowledgedbytheEEPROM,themicrocontrollermustgenerateanotherstartcondition.Themicrocontrollernow initiatesa currentaddressreadbysendingadeviceaddresswiththeread/writeselectbithigh.TheEEPROMacknowledgesthedeviceaddressandseriallyclocksoutthedataword.Themicrocontrollerdoesnotrespondwith a"o"(NOACK)butdoesgeneratea followingstopcondition (refertoFigure10)Figure10.RandomReadWRITESTARTSTASTOPREADDEVICEWORDDEVICEADDRESSR2ADDRESSADDRESSnSDALINEMSBzo2AMSBLSBACKDATAnBWKBJKACKDUMMY WRITENote:*=DON'TCAREbitfor1K)TMEL91610B-SEEPR-04/04

9 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 will the EEPROM respond with a “0” (ACK), allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations, with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read, and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover” during read is from the last byte of the last memory page to the first byte of the first page. The address “rollover” during write is from the last byte of the cur￾rent page to the first byte of the same page. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (refer to Figure 9) Figure 9. Current Address Read. RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” (NO ACK) but does generate a following stop condition (refer to Figure 10). Figure 10. Random Read Note: * = DON’T CARE bit for 1K) S T A R T SDA LINE M S B L S B R / W A C K DATA N O A C K DEVICE ADDRESS R E A D WORD ADDRESS n L S B A C K M S B L S B

AMELSEQUENTIALREAD:Sequential readsareinitiatedbyeitheracurrentaddressreadorarandomaddressread.Afterthemicrocontrollerreceives adataword,it respondswithanacknowledge.AslongastheEEPROMreceivesanacknowledge,itwillcontinuetoincrementthedatawordaddressandseriallyclockoutsequentialdatawords.Whenthememoryaddress limitis reached,thedata word addresswill"rollover"and thesequen-tial read will continue.The sequential read operation is terminated when themicrocontrollerdoes not respondwith a"o"(NO ACK)butdoesgeneratea followingstopcondition(refertoFigure11)Figure11.SequentialRead:STOPREADACKACKACKDEVICEADDRESSFSDA LINELzo蒙DATAnDATA n + 1DATA n + 2DATAn + 3ACKAT24C01ASC/02SC/04SC/08SC/16SC101610B-SEEPR04/04

10 AT24C01ASC/02SC/04SC/08SC/16SC 1610B–SEEPR–04/04 SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “rollover” and the sequen￾tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” (NO ACK) but does generate a following stop condition (refer to Figure 11). Figure 11. Sequential Read