《嵌入式应用开发》课程教学资源（文献资料）W25Q64BV 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q64BVwinbondSpiFlash64M-BITSERIALFLASHMEMORYWITHDUALANDOUADSPIwinbond25Q64BVFIGVInbABVSIIC25Q64BPublicationReleaseDate:July08,2010RevisionE

W25Q64BV Publication Release Date: July 08, 2010 - 1 - Revision E 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25064BVwinbondTableof Contents1.GENERALDESCRIPTION52..5FEATURES3..6PINCONFIGURATIONSOIC208-MIL4..6PADCONFIGURATIONWSON8X6-MM5.PADCONFIGURATIONPDIP300-MIL6..7PINDESCRIPTIONSOIC208-MILPDIP300-MILANDWSON8X6-MM7...8PINCONFIGURATIONSOIC3O0-MIL8.PINDESCRIPTIONSOIC300-MIL88.1..9PackageTypes..8.2.9ChipSelect (/CS)8.3..9SerialDataInput,Outputand1Os(Dl,D0and100,101,102,103)8.4WriteProtect(WP)...98.5HOLD (/HOLD).98.69SerialClock(CLK)9.BLOCK DIAGRAM.1010.FUNCTIONALDESCRIPTION.111110.1SPIOPERATIONS10.1.1StandardSPIInstructions.1110.1.2Dual SPIInstructions.1110.1.3QuadSPIInstructions1110.1.4Hold Function1110.2WRITEPROTECTION1210.2.1WriteProtectFeatures1211.13CONTROLANDSTATUSREGISTERS1311.1STATUSREGISTER11.1.1BUSY.1311.1.2.13Write Enable Latch (WEL).11.1.313BlockProtectBits(BP2,BP1,BPO)11.1.4Top/BottomBlockProtect(TB).1311.1.5Sector/BlockProtect(SEC)..1311.1.6StatusRegisterProtect (SRP1,SRPO).1411.1.7QuadEnable(QE).1411.1.8.16StatusRegisterMemoryProtection11.2INSTRUCTIONS...1711.2.1ManufacturerandDeviceldentification.1711.2.2.18InstructionSetTable1.- 2 -

W25Q64BV - 2 - Table of Contents 1. GENERAL DESCRIPTION.5 2. FEATURES.5 3. PIN CONFIGURATION SOIC 208-MIL .6 4. PAD CONFIGURATION WSON 8X6-MM .6 5. PAD CONFIGURATION PDIP 300-MIL .7 6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL AND WSON 8X6-MM.7 7. PIN CONFIGURATION SOIC 300-MIL .8 8. PIN DESCRIPTION SOIC 300-MIL .8 8.1 Package Types.9 8.2 Chip Select (/CS).9 8.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .9 8.4 Write Protect (/WP).9 8.5 HOLD (/HOLD) .9 8.6 Serial Clock (CLK).9 9. BLOCK DIAGRAM.10 10. FUNCTIONAL DESCRIPTION .11 10.1 SPI OPERATIONS .11 10.1.1 Standard SPI Instructions.11 10.1.2 Dual SPI Instructions.11 10.1.3 Quad SPI Instructions.11 10.1.4 Hold Function .11 10.2 WRITE PROTECTION .12 10.2.1 Write Protect Features.12 11. CONTROL AND STATUS REGISTERS .13 11.1 STATUS REGISTER.13 11.1.1 BUSY.13 11.1.2 Write Enable Latch (WEL).13 11.1.3 Block Protect Bits (BP2, BP1, BP0).13 11.1.4 Top/Bottom Block Protect (TB).13 11.1.5 Sector/Block Protect (SEC) .13 11.1.6 Status Register Protect (SRP1, SRP0).14 11.1.7 Quad Enable (QE).14 11.1.8 Status Register Memory Protection.16 11.2 INSTRUCTIONS.17 11.2.1 Manufacturer and Device Identification .17 11.2.2 Instruction Set Table 1.18

W25064BVwinbond11.2.3InstructionSetTable2(ReadInstructions)1911.2.420Write Enable (06h)....2011.2.5WriteDisable(04h)11.2.6ReadStatus Register-1(05h)and Read Status Register-2 (35h)..2111.2.7..22WriteStatusRegister (01h)11.2.8Read Data (03h)..2311.2.9FastRead (OBh)..24..2511.2.10FastReadDualOutput (3Bh)11.2.11FastReadQuadOutput(6Bh).2611.2.12Fast Read Dual I/O (BBh)..2711.2.13.29FastReadQuadVO(EBh)11.2.14OctalWordReadQuadVO(E3h).3111.2.15.33PageProgram(02h).11.2.16Quad InputPageProgram (32h).3411.2.17SectorErase(20h).3511.2.1832KBBlockErase (52h).3611.2.1964KBBlockErase (D8h).3711.2.2038ChipErase(C7h/60h)11.2.21.39EraseSuspend (75h)..11.2.2240EraseResume(7Ah).11.2.23Power-down (B9h).....4111.2.24.42HighPerformanceMode(A3h)11.2.25ReleasePower-downorHighPerformanceMode/DeviceID(ABh).4211.2.26.44Read Manufacturer/Device ID (90h)11.2.27ReadUniqueIDNumber (4Bh).4511.2.28ReadJEDECID (9Fh)....4611.2.29.47ContinuousReadModeReset (FFhorFFFFh)12..48ELECTRICALCHARACTERISTICS12.1...48Absolute Maximum Ratings..12.2.48OperatingRanges12.3..49Power-up Timing and Write Inhibit Threshold12.4DC Electrical Characteristics...5012.5AC Measurement Conditions .....5112.6..52Ac Electrical Characteristics.12.7...53ACElectricalCharacteristics(cont'd)12.8..54Serial Output Timing.12.9...54Input Timing.12.10...54Hold Timing13.PACKAGE SPECIFICATION...55Publication ReleaseDate:July 08.2010-3 -RevisionE

W25Q64BV 11.2.3 Instruction Set Table 2 (Read Instructions) .19 Publication Release Date: July 08, 2010 - 3 - Revision E 11.2.4 Write Enable (06h).20 11.2.5 Write Disable (04h).20 11.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h).21 11.2.7 Write Status Register (01h) .22 11.2.8 Read Data (03h).23 11.2.9 Fast Read (0Bh).24 11.2.10 Fast Read Dual Output (3Bh).25 11.2.11 Fast Read Quad Output (6Bh).26 11.2.12 Fast Read Dual I/O (BBh).27 11.2.13 Fast Read Quad I/O (EBh) .29 11.2.14 Octal Word Read Quad I/O (E3h).31 11.2.15 Page Program (02h).33 11.2.16 Quad Input Page Program (32h) .34 11.2.17 Sector Erase (20h) .35 11.2.18 32KB Block Erase (52h) .36 11.2.19 64KB Block Erase (D8h).37 11.2.20 Chip Erase (C7h / 60h).38 11.2.21 Erase Suspend (75h).39 11.2.22 Erase Resume (7Ah).40 11.2.23 Power-down (B9h).41 11.2.24 High Performance Mode (A3h).42 11.2.25 Release Power-down or High Performance Mode / Device ID (ABh) .42 11.2.26 Read Manufacturer / Device ID (90h).44 11.2.27 Read Unique ID Number (4Bh).45 11.2.28 Read JEDEC ID (9Fh).46 11.2.29 Continuous Read Mode Reset (FFh or FFFFh).47 12. ELECTRICAL CHARACTERISTICS .48 12.1 Absolute Maximum Ratings.48 12.2 Operating Ranges .48 12.3 Power-up Timing and Write Inhibit Threshold.49 12.4 DC Electrical Characteristics.50 12.5 AC Measurement Conditions .51 12.6 AC Electrical Characteristics.52 12.7 AC Electrical Characteristics (cont’d).53 12.8 Serial Output Timing.54 12.9 Input Timing.54 12.10 Hold Timing.54 13. PACKAGE SPECIFICATION.55

W25Q64BVwinbond13.18-Pin SOIC 208-mil (Package Code SS)..5513.2...568-Pin PDIP 300-mil (Package Code DA).13.38-Contact8x6mmWSON (PackageCodeZE)...57...5813.416-PinSOIC300-mil (PackageCodeSF)14...59ORDERINGINFORMATION..6014.1ValidPartNumbersandTopSideMarking15.REVISIONHISTORY.61

W25Q64BV 13.1 8-Pin SOIC 208-mil (Package Code SS) .55 - 4 - 13.2 8-Pin PDIP 300-mil (Package Code DA).56 13.3 8-Contact 8x6mm WSON (Package Code ZE).57 13.4 16-Pin SOIC 300-mil (Package Code SF).58 14. ORDERING INFORMATION .59 14.1 Valid Part Numbers and Top Side Marking.60 15. REVISION HISTORY.61

W25Q64BVwinbond1.GENERALDESCRIPTIONTheW25Q64BV(64M-bit)SerialFlashmemoryprovidesastoragesolutionforsystemswithlimitedspace,pinsandpower.The25Qseriesoffersflexibilityandperformancewell beyondordinarySerialFlash devices.Theyare ideal for code shadowing toRAM,executing codedirectlyfromDual/Quad SPl(XiP)andstoringvoice,textanddata.Thedevicesoperateonasingle2.7Vto3.6Vpowersupplywithcurrentconsumptionas lowas4mAactiveand1μAforpower-down.Alldevices areofferedinspace-savingpackages.The W25Q64BV array is organized into 32,768 programmable pages of 256-bytes each.Up to 256 bytescanbeprogrammedatatime.Pagescanbeerasedingroupsof16(sectorerase),groupsof128(32KBblockerase)groupsof256(64KBblockerase)ortheentirechip(chiperase).TheW25Q64BVhas2.048erasablesectors and128erasableblocks respectively.Thesmali 4KBsectors allowforgreaterflexibilityinapplicationsthatrequiredataandparameterstorage.(Seefigure2.)The W25Q64BVsupportsthe standardSerialPeripheralInterface (SPI),anda highperformanceDual/Quad outputas well asDual/QuadVOSPl:Serial Clock,ChipSelect, Serial Data VOo (DI),IV/O1(DO), V/O2 (WP), and I/O3 (/HOLD). SPI clock frequencies of up to 80MHz are supported allowingequivalentclockratesof160MHzforDualOutputand320MHzforQuadOutputwhenusingtheFastReadDual/QuadOutputinstructions.ThesetransferratescanoutperformstandardAsynchronous8and16-bitParallelFlashmemories.TheContinuousReadModeallowsforefficientmemoryaccesswithasfewas8-clocks of instruction-overheadtoreada24-bitaddress,allowingtrueXiP(execute inplace)operation.AHold pin,WriteProtectpin and programmablewrite protection,withtop orbottomarraycontrolprovide further control flexibility.Additionally.the device supports JEDEC standard manufacturer anddeviceidentificationwitha64-bitUniqueSerialNumber.2.FEATURES·FamilyofSpiFlashMemories.LowPower,WideTemperatureRange-W25Q64BV:64M-bit/8M-byte(8.388.608)-Single2.7to3.6V supply-256-bytesperprogrammablepage-4mAactivecurrent,<1μAPower-down(typ.)--40°Cto+85CoperatingrangeStandard,Dual orQuadSPI-Standard SPI:CLK,/CS,DI, DO,WP,/HoldFlexibleArchitecturewith4KBsectors-Dual SPI:CLK,/CS, IOo, IO1,WP,/Hold-UniformSectorErase(4K-bytes)-QuadSPI:CLK,/CS,1O0,1O1,1O2,103-BlockErase(32Kand64K-bytes)-Programone to256bytes.HighestPerformanceSerialFlash-Morethan100.000erase/writecycles-Upto6XthatofordinarySerialFlash-Morethan20-yeardataretention-80MHzclockoperation-160MHzequivalentDualSPIAdvancedSecurityFeatures-320MHz equivalentQuad SPI-SoftwareandHardwareWrite-Protect-40MB/Scontinuousdatatransferrate-ToporBottom,SectororBlockselection-Lock-DownandOTPprotection(1.Efficient"ContinuousRead Mode'-64-Bit Unique ID for each device(1)-Lowlnstructionoverhead.SpaceEfficient Packaging-Asfewas8clockstoaddressmemory-AllowstrueXiP(executeinplace)operation-8-pinSOIC208-mil-8-pinPDIP300-mil-OutperformsX16ParallelFlash-8-padWSON8x6-mm-16-pinSOIC300-milNote1:ContactWinbondfordetails-ContactWinbondforKGDandotheroptionsPublicationReleaseDate:July08.2010-5-RevisionE

W25Q64BV Publication Release Date: July 08, 2010 - 5 - Revision E 1. GENERAL DESCRIPTION The W25Q64BV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space￾saving packages. The W25Q64BV array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q64BV has 2,048 erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q64BV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the Fast Read Dual/Quad Output instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES • Family of SpiFlash Memories – W25Q64BV: 64M-bit / 8M-byte (8,388,608) – 256-bytes per programmable page • Standard, Dual or Quad SPI – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 • Highest Performance Serial Flash – Up to 6X that of ordinary Serial Flash – 80MHz clock operation – 160MHz equivalent Dual SPI – 320MHz equivalent Quad SPI – 40MB/S continuous data transfer rate • Efficient “Continuous Read Mode” – Low Instruction overhead – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash Note 1: Contact Winbond for details • Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40°C to +85°C operating range • Flexible Architecture with 4KB sectors – Uniform Sector Erase (4K-bytes) – Block Erase (32K and 64K-bytes) – Program one to 256 bytes – More than 100,000 erase/write cycles – More than 20-year data retention • Advanced Security Features – Software and Hardware Write-Protect – Top or Bottom, Sector or Block selection – Lock-Down and OTP protection(1) – 64-Bit Unique ID for each device(1) • Space Efficient Packaging – 8-pin SOIC 208-mil – 8-pin PDIP 300-mil – 8-pad WSON 8x6-mm – 16-pin SOIC 300-mil – Contact Winbond for KGD and other options

W25Q64BVwinbond3.PINCONFIGURATIONSOIC208-MILICS0VCC827DO (IO,)/HOLD (IO3)MP (IO2)CLK36GND45DI (IO)Figure 1a. W25Q64BV Pin Assignments, 8-pin SOIC 208-mil(Package Code SS)4.PADCONFIGURATIONWSON8X6-MMD018CVCCICS27 CDO (IO,)/HOLD (IO3)D36CCLKP (IO2)GND045CDI (IO)Figure 1b.W25Q64BV Pad Assignments,8-pad WSON 8x6-mm(Package Code ZE)-6-

W25Q64BV - 6 - 3. PIN CONFIGURATION SOIC 208-MIL 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) Figure 1a. W25Q64BV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 8X6-MM 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) Figure 1b. W25Q64BV Pad Assignments, 8-pad WSON 8x6-mm(Package Code ZE)

W25Q64BVwinbond5.PADCONFIGURATIONPDIP300-MIL018ICSVCC27DO (IO)/HOLD (IO3)MP (IO2)36CLK54GNDDI (IO0)Figure 1c. W25Q64BV Pin Assignments, 8-pin PDIP (Package Code DA)6.PINDESCRIPTIONSOIC208-MIL,PDIP300-MILANDWSON8X6-MMVOPIN NO.PIN NAMEFUNCTION1ICS1Chip Select Input2VODO (IO1)Data Output (Data Input Output 1)*13IVOWP (IO2)WriteProtectInput(DataInputOutput2)*4GNDGround5IVODI (IO0)Data Input (Data Input Output 0)*16CLK1Serial Clock Input7VOHold Input (Data Input Output 3)*2/HOLD (IO3)8VCCPowerSupply*1IO0andIO1areusedforStandardandDualSPIinstructions*2IO0-103areusedforQuadSPlinstructionsPublicationReleaseDate:July08,2010-7.RevisionE

W25Q64BV Publication Release Date: July 08, 2010 - 7 - Revision E 5. PAD CONFIGURATION PDIP 300-MIL 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) Figure 1c. W25Q64BV Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL AND WSON 8X6-MM PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input 2 DO (IO1) I/O Data Output (Data Input Output 1)*1 3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2 4 GND Ground 5 DI (IO0) I/O Data Input (Data Input Output 0)*1 6 CLK I Serial Clock Input 7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 8 VCC Power Supply *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

W25Q64BVwinbondPINCONFIGURATIONSOIC300-MIL7.0116/HOLD (IO.)CLK215VCCDI (IO)314N/C2N/CD13N/C4N/C>LN/C512N/CCO611N/CDN/C7ICS10GND89DO (O,)MP (IO2)DFigure1d.W25Q64BVPinAssignments,16-pin SOIC 300-mil (PackageCode SF)8.PINDESCRIPTIONSOIC300-MILVOPAD NO.PAD NAMEFUNCTION1VOHold Input (Data Input Output 3)*2/HOLD (IO3)2vCCPowerSupply3N/CNoConnect4N/CNoConnect5N/CNo Connect6N/CNoConnect7ICS-Chip Select Input8VOData Output (Data Input Output 1)*1DO (IO1)9VOWP (IO2)Write Protect Input (Data Input Output 2)*210GNDGround11N/CNo Connect12N/CNoConnect13N/CNo Connect14N/CNo Connect15VODI (IO0)Data Input (Data Input Output 0)*116CLK1Serial Clock Input*1IO0andIO1areusedforStandardandDualSPIinstructions*2IO0-1O3areusedforQuadSPIinstructions- 8 -

W25Q64BV - 8 - 7. PIN CONFIGURATION SOIC 300-MIL /HOLD (IO3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC N/C N/C N/C N/C /CS DO (IO ) CLK DI (IO0) N/C N/C N/C N/C GND /WP (IO ) 1 2 /HOLD (IO3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC N/C N/C N/C N/C /CS DO (IO ) CLK DI (IO0) N/C N/C N/C N/C GND /WP (IO ) 1 2 Figure 1d. W25Q64BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 8. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 2 VCC Power Supply 3 N/C No Connect 4 N/C No Connect 5 N/C No Connect 6 N/C No Connect 7 /CS I Chip Select Input 8 DO (IO1) I/O Data Output (Data Input Output 1)*1 9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 10 GND Ground 11 N/C No Connect 12 N/C No Connect 13 N/C No Connect 14 N/C No Connect 15 DI (IO0) I/O Data Input (Data Input Output 0)*1 16 CLK I Serial Clock Input *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

W25Q64BVwinbond8.1PackageTypesW25Q64BVisofferedinan8-pinplastic208-milwidthSOIC(packagecodeSS)and8x6-mmWSON(packagecodeZE)asshowninfigure1a,and1b,respectively.The300-mil8-pinPDiPisanotheroptionofpackageselections(Figure1c).TheW25Q64BVisalsoofferedina16-pinplastic300-milwidthSOIC(packagecodeSF)asshowninfigure1d.Packagediagramsanddimensionsareillustratedattheendofthis datasheet.8.2 ChipSelect(/CS)The SPI Chip Select (/CS) pin enables and disables device operation. When /Cs is high the device isdeselectedand the SerialData Output(DO,or1O0,101,102,0O3)pins are athighimpedance.Whendeselected,thedevicespowerconsumptionwill beatstandbylevelsunlessan internalerase,programorstatus register cycle is inprogress.WhenIcs isbrought lowthedevicewill be selected,powerconsumptionwill increaseto activelevelsandinstructionscanbewrittentoanddatareadfromthedevice.Afterpower-up,/csmusttransitionfromhightolowbeforeanewinstructionwill beaccepted.TheICSinputmusttracktheVCCsupplylevelatpower-up(see"WriteProtection"andfigure31).Ifneededapull-upresisteron/cscanbeusedtoaccomplishthis.8.3SerialDatalnput,Outputand1Os(Dl,D0and100,101,102,103)TheW25Q64BVsupports standardSPI,Dual SPIandQuadSPIoperation.StandardSPIinstructionsusethe unidirectional Dl (input)pinto seriallywriteinstructions,addressesordatatothedeviceontherisingedgeoftheSerialClock(CLK)inputpin.StandardSPIalsousestheunidirectionalDO(output)toreaddataorstatusfromthedeviceonthefallingedgeCLK.Dual and Quad SPl instruction use the bidirectional IO pins to serially write instructions,addresses ordatatothedeviceontherisingedgeofCLKand readdataorstatusfromthedeviceonthefallingedgeofCLK.QuadSPIinstructionsrequirethenon-volatileQuadEnablebit(QE)inStatusRegister-2tobeset.WhenQE=1theWPpinbecomesIO2and/HOLDpinbecomesIO3.8.4WriteProtect(/WP)The Write Protect (WP) pin can be used to prevent the Status Register from being written. Used inconjunctionwiththeStatusRegister'sBlockProtect(SEC,TB,BP2,BP1andBPO)bitsandStatusRegisterProtect(SRP)bits,aportionortheentirememoryarraycanbehardwareprotected.TheWPpinisactivelow.WhentheQEbitofStatusRegister-2issetforQuadI/O.theWPpin(HardwareWriteProtect)functionisnotavailablesincethispinisusedforIO2.Seefigure1a,1b,1cand1dforthepinconfigurationofQuadI/Ooperation.8.5HOLD(/HOLD)The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,while /CS is iow,the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored(don'tcare).When/HOLD isbroughthigh,deviceoperationcanresume.The/HOLDfunctioncanbeuseful whenmultipledevicesaresharingthesameSPIsignals.The/HOLDpinisactivelow.WhentheQEbitof StatusRegister-2is setforQuad V/O,the/HOLD pinfunction isnotavailablesincethispinisusedforIO3.Seefigure1a-dforthepinconfigurationofQuadI/Ooperation.8.6 Serial Clock (CLK)TheSPISerialClockInput(CLK)pinprovidesthetimingforserial inputandoutputoperations.("SeeSPIOperations")PublicationReleaseDate:July08,2010- 9 -RevisionE

W25Q64BV Publication Release Date: July 08, 2010 - 9 - Revision E 8.1 Package Types W25Q64BV is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 8x6-mm WSON (package code ZE) as shown in figure 1a, and 1b, respectively. The 300-mil 8-pin PDIP is another option of package selections (Figure 1c). The W25Q64BV is also offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1d. Package diagrams and dimensions are illustrated at the end of this datasheet. 8.2 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 31). If needed a pull-up resister on /CS can be used to accomplish this. 8.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q64BV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3. 8.4 Write Protect (/WP) The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2. See figure 1a, 1b, 1c and 1d for the pin configuration of Quad I/O operation. 8.5 HOLD (/HOLD) The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a-d for the pin configuration of Quad I/O operation. 8.6 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")

W25Q64BVwinbond9.BLOCKDIAGRAMBlockSentation7FFF0Oh7FFFFFhxxFF00hxxFFFFhBlock 127 (64KB)Sector 15 (4KB)7F0000h7F00FFhxxF000hxxFOFFhxxEF00hxxEFFFhSector 14 (4KB)xxE000hxxEOFFhxxDF0OhxxDFFFhSector 13 (4KB)xxD000hxxDOFFh.eooaoxx2F00hxx2FFFhSector 2 (4KB)Oxx20FFhx2000h40FF00h40FFFFhxx1F00hxx1FFFh0Block 64 (64KB)pueSector 1 (4KB)400000h4000FFhxx1000hxx10FFhxx0F0Ohxx0FFFh3FFF00h3FFFFFhSector 0 (4KB)Block 63 (64KB)2xx0000hxx00FFh3F0000h3F00FFhnmsnnnmsnnnmsnnnmsnnn.Write ControlWP (102) 4Logic20FF00h20FFFFhBlock 32 (64KB)200000h2000FFhStatus1FFF00h1FFFFFhRegisterBlock 31 (64KB)1F00FFh1F00004?High VoltageGenerators00FF00hOOFFFFhBlock 0 (64KB)/HOLD (IO)4000000h0000FFh Page AddressCLKLatch/CounterIBeginningEndingSPIPage AddressPage AddressICSCommand&Control LogicColumnDecodeAnd 256-Byte Page BufferDataDI (IO)DO (IO,)Byte AddressLatch/CounterFigure2.W25Q64BVSerial FlashMemoryBlockDiagram- 10 -

W25Q64BV - 10 - 9. BLOCK DIAGRAM Figure 2. W25Q64BV Serial Flash Memory Block Diagram 00FF00h 00FFFFh • Block 0 (64KB) • 000000h 0000FFh • • • 1FFF00h 1FFFFFh • Block 31 (64KB) • 1F0000h 1F00FFh 20FF00h 20FFFFh • Block 32 (64KB) • 200000h 2000FFh • • • 3FFF00h 3FFFFFh • Block 63 (64KB) • 3F0000h 3F00FFh 40FF00h 40FFFFh • Block 64 (64KB) • 400000h 4000FFh • • • 7FFF00h 7FFFFFh • Block 127 (64KB) • 7F0000h 7F00FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q64BV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter High Voltage Generators xx0F00h xx0FFFh • Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh • Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh • Sector 2 (4KB) • xx2000h xx20FFh • • • xxDF00h xxDFFFh • Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh • Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh • Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode DO (IO1) DI (IO0) /CS CLK /HOLD (IO3) /WP (IO2) 00FF00h 00FFFFh • Block 0 (64KB) • 000000h 0000FFh • • • 1FFF00h 1FFFFFh • Block 31 (64KB) • 1F0000h 1F00FFh 20FF00h 20FFFFh • Block 32 (64KB) • 200000h 2000FFh • • • 3FFF00h 3FFFFFh • Block 63 (64KB) • 3F0000h 3F00FFh 40FF00h 40FFFFh • Block 64 (64KB) • 400000h 4000FFh • • • 7FFF00h 7FFFFFh • Block 127 (64KB) • 7F0000h 7F00FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q64BV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter High Voltage Generators xx0F00h xx0FFFh • Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh • Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh • Sector 2 (4KB) • xx2000h xx20FFh • • • xxDF00h xxDFFFh • Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh • Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh • Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode DO (IO1) DI (IO0) /CS CLK /HOLD (IO3) /WP (IO2)