《数字电》英文版 chapter4-5 Flip-flops

Flip-flops Chapter4 Register

Flip-flops Chapter4 Register

"s· Registers, formed from a collection of flip-flops, are used to store or manipulate data or both a Input and output function associated with registers include D Parallel input/ Parallel output a Serial input serial output a Parallel input Serial output a Serial input parallel output

◼ Registers, formed from a collection of flip-flops, are used to store or manipulate data or both. ◼ Input and output function associated with registers include Parallel input / Parallel output Serial input / Serial output Parallel input / Serial output Serial input / parallel output

"s· Sim ple 1-bit register a Flip-flops have two stable Qi Qi state can store binary code Read a One flip-flop Store can only store C Receive one binary bit D RD Clear

◼ Flip-flops have two stable state, can store binary code. ◼ One flip-flop can only store one binary bit. D Q’ Q C Di Qi Qi’ Store Read Clear RD Receive Simple 1-bit register

"s· Shift Register a Serial input Serial output Shift register a Universal Shift register ■SN74Ls194 a Parallel input /parallel output a Four parallel data inputs permit parallel loading ofeⅹ ternal data a Two serial input one for left-shift, and the other for right-shift O Serial output data are taken from either QA(LSB)or QD(MSB) depending on shift direction

Shift Register ◼ Serial input / Serial output Shift register ◼ Universal Shift Register ◼ SN74LS194  Parallel input / parallel output  Four Parallel data inputs permit parallel loading of external data.  Two serial input, one for left-shift, and the other for right-shift.  Serial output data are taken from either QA(LSB) or QD(MSB) depending on shift direction

Figure 5. 104(page 302) QA QB Qc QD Positive edge triggered SO CLR a Two serial input: s0, S1 CLK S1 CLR can clear the data freely SR A B C D SL Combined with clock pulse D SOS1=11. load the external data D SOS1=10, shift right, (QA QBQCQDn+l=(SRQA QBQcn 口S0S1=10, shift left (QA QBQCQDn+l=(QBQCQDSL 口5S1=00. inhibit

◼ Figure 5.104 (page 302) ◼ Positive edge triggered ◼ Two serial input: S0, S1 ◼ CLR can clear the data freely ◼ Combined with clock pulse  S0S1=11, load the external data  S0S1=10, shift right, ◼ (QAQBQCQD) n+1=(SRQAQBQC ) n  S0S1=10, shift left, ◼ (QAQBQCQD) n+1=(QBQCQDSL)n  S0S1=00, inhibit SR A B C D SL CLK QA QB QC QD CLR S0 S1

Homework 5.6 19 333539

Homework ◼5,6 ◼19 ◼33,35,39