复旦大学：《计算机原理 Computer System》课程PPT课件_09、10 Sequential CPU Implementation

Sequential CPU Implementation

Sequential CPU Implementation

Suggested Reading Chap 4.3 Processor

– 2 – Processor Suggested Reading - Chap 4.3

Y86 Instruction Set P259 Byte 00 addl halt subl rrmovl rA, rB P2|0旧 and16 irmov1V rB rmmovl rA, d(rB)40 rB D mrmovl D(rB), TA [50 TA rB D e OPl rA, rB 6 n[ rBh 1[2 jXX Dest Dest e all dest Dest ne ret pushl rA Ara 8 g WI Tod c- 0|rA8 Processor

– 3 – Processor Y86 Instruction Set P259 Byte 0 1 2 3 4 5 pushl rA A 0 rA 8 jXX Dest 7 fn Dest popl rA B 0 rA 8 call Dest 8 0 Dest rrmovl rA, rB 2 0 rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D mrmovl D(rB), rA 5 0 rA rB D OPl rA, rB 6 fn rA rB ret 9 0 nop 0 0 halt 1 0 addl 6 0 subl 6 1 andl 6 2 xorl 6 3 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6

Building Blocks p278, P279,P280 fun Combinational Logic A A Compute Boolean functions of Inputs a Continuously respond to input changes MUX a Operate on data and im plement control Storage Elements ■ Store bits SrcA/A Registe dst a Addressable memories Non-addressable registers srcB Clock a Loaded only as clock rises Clock Processor

– 4 – Processor Building Blocks P278, P279, P280 Combinational Logic ◼ Compute Boolean functions of inputs ◼ Continuously respond to input changes ◼ Operate on data and implement control Storage Elements ◼ Store bits ◼ Addressable memories ◼ Non-addressable registers ◼ Loaded only as clock rises Register file A B W dstW srcA valA srcB valB valW Clock A L U fun A B MUX 0 1 = Clock

Hardware Control Language a Very simple hardware description language a Can only express limited aspects of hardware operation e Parts we want to explore and modify Data Types ■boo1: Boolean a, b, C,.. int: words ●A,B,C, e Does not specify word size---bytes, 32-bit words, Statements bool a= bool-expr i nt a int-expr i 5 Processor

– 5 – Processor Hardware Control Language ◼ Very simple hardware description language ◼ Can only express limited aspects of hardware operation ⚫ Parts we want to explore and modify Data Types ◼ bool: Boolean ⚫ a, b, c, … ◼ int: words ⚫ A, B, C, … ⚫ Does not specify word size---bytes, 32-bit words, … Statements ◼ bool a = bool-expr ; ◼ int A = int-expr ;

HCL Operations a Classify by type of value returned Boolean Expressions ■ Logic Operations ●a&&b,al|b,! ■ Word com parisons OA == B,A != B,A B,A>B ■ Set Mem bership A in[ B, C,d 1 ) Same asA== B 二二 Word Expressions a Case expressions A b: B: C: C] O Evaluate test expressions a, b, C,.. in sequence o Return word expression A, B, C,. for first successful test Processor

– 6 – Processor HCL Operations ◼ Classify by type of value returned Boolean Expressions ◼ Logic Operations ⚫ a && b, a || b, !a ◼ Word Comparisons ⚫ A == B, A != B, A = B, A > B ◼ Set Membership ⚫ A in { B, C, D } » Same as A == B || A == C || A == D Word Expressions ◼ Case expressions ⚫ [ a : A; b : B; c : C ] ⚫ Evaluate test expressions a, b, c, … in sequence ⚫ Return word expression A, B, C, … for first successful test

43.1 Instruction Execution Stages P281 Fetch a Read instruction from instruction memory Decode a Read program registers Execute a Compute value or address Memory ■ Read or write data Write Back a Write program registers PC a Update program counter Processor

– 7 – Processor 4.3.1 Instruction Execution Stages P281 Fetch ◼ Read instruction from instruction memory Decode ◼ Read program registers Execute ◼ Compute value or address Memory ◼ Read or write data Write Back ◼ Write program registers PC ◼ Update program counter

Instruction Decoding Optional Optional 50rAIrB D icode ifun TA B valc Instruction Format ■ nstruction byte icode: ifun a Optional register byte rA: rB a Optional constant word valC 8 Processor

– 8 – Processor Instruction Decoding Instruction Format ◼ Instruction byte icode:ifun ◼ Optional register byte rA:rB ◼ Optional constant word valC 5 0 rA rB D icode ifun rA rB valC Optional Optional

Figure 4.16 P283 Executing Arith /Logical Operation OPl rA, rB 6 fn ralrB Fetch Memory Read 2 bytes Do nothing Decode Write back Read operand registers ■ Update register Execute PC Update ■ Perform operation ■ Increment Pc by2 Set condition codes -9 Processor

– 9 – Processor Figure 4.16 P283 Executing Arith./Logical Operation Fetch ◼ Read 2 bytes Decode ◼ Read operand registers Execute ◼ Perform operation ◼ Set condition codes Memory ◼ Do nothing Write back ◼ Update register PC Update ◼ Increment PC by 2 OPl rA, rB 6 fn rA rB

Stage Computation: Arith/Log. Ops P283 igure 4.16 OPl A, rB icode:ifun←-M1[Pc] Read instruction byte rA:rB←M1[Pc+们 Read register byte Fetch vaIP tPC+2 Compute next PC vaA←R[A Read operand a Decode vaB←R[rB] Read operand B vale t valB oP valA Perform ALU operation Execute Set cc Set condition code register Memory Write RrB]←vaE Write back result back PC update PC←vaP Update Pc a Formulate instruction execution as sequence of simple steps a Use same general form for all instructions 10-MPC]表示从PC开始的内存中读取一个字节的数据 Processor

– 10 – Processor Stage Computation: Arith/Log. Ops P283 Figure 4.16 ◼ Formulate instruction execution as sequence of simple steps ◼ Use same general form for all instructions OPl rA, rB icode:ifun  M1 [PC] rA:rB  M1 [PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory Write R[rB]  valE back Write back result PC update PC  valP Update PC M1 [PC] 表示从PC开始的内存中读取一个字节的数据