电子科技大学：《电子设计自动化技术》课程教学资源（讲义课件）基本术语（李平）

电子设计自动化技术 补充内容

电子设计自动化技术 补充内容

基本术语 EDa( Electronic Design automation ASIC (Application Specific Integrated Circuit) FPGA( Field Programmable Gate-array) CPLD( Complex Programmable Logic Device) Soc System On a chip) IP(Intellectual Property) ISP(In-System Programmable

基本术语 „ EDA（Electronic Design Automation） „ ASIC（Application Specific Integrated Circuit） „ FPGA（Field Programmable Gate-Array） „ CPLD（Complex Programmable Logic Device） „ SOC（System On a Chip） „ IP（Intellectual Property） „ ISP（In-System Programmable ）

基本术语 Front-end(前端) ■Back-end(后端) a PcB( Printed circuit board) MPU(MicroProcessor Unit) DSP( Digital Signal Processor/Processing) RoM( Read Only Memory) sRAM(Static Random Access Memory) EEPROM Electrically Erasable Programmable rom)

基本术语 „ Front-end（前端） „ Back-end（后端） „ PCB （Printed Circuit Board） „ MPU （MicroProcessor Unit） „ DSP （Digital Signal Processor/Processing） „ ROM （Read Only Memory） „ SRAM （Static Random Access Memory） „ EEPROM （Electrically Erasable Programmable ROM）

VHDL的三大要点 VHDL程序的基本结构 Signal与 Variable的比较

VHDL的三大要点 „ VHDL程序的基本结构 „ Signal与Variable的比较

Signal VS Variable

Signal vs Variable

ignal vs Variabl e Signal assignment(<=) receive the assign value after a period ot t ime Variable assignment happens immediately when the statement is executed, no delay (3)

Signal vs Variable „ Signal Assignment (<= ) „ receive the assign value after a period of time „ Variable Assignment „ happens immediately when the statement is executed, no delay (: = )

Key points to remember Function Variables represent local storage Variables is updated immediately the updated value can be used later in the model for further computations Signals represent circuit interconnect Place of declare Variables: Process, Function Procedure Signal Architecture, Package, Entity

Key points to remember „ Function „ Variables represent local storage „ Variables is updated immediately „ the updated value can be used later in the model for further computations „ Signals represent circuit interconnect „ Place of Declare „ Variables : Process, Function,Procedure „ Signal : Architecture,Package,Entity

Visible Variable Signal if define within Entity -visible within the whole Entity if define within architecture-visible Within the whole architecture if define within package -visible within the whole package Make sure that you must have the correct Signal or variable declaration

„ Visible „ Variable „ Signal : if define within Entity - visible within the whole Entity if define within Architecture - visible within the whole Architecture if define within Package - visible within the whole Package „ Make sure that you must have the correct Signal or Variable declaration

Data Type VHDL Is a strongly DATA TYPE ORIENT LANGUAGE

Data Type VHDL is a strongly DATA TYPE ORIENT LANGUAGE

Type Data VHDL is a very rigid type data oriented language Q: What is it means? A: Different type can not do ar iny assignment e. g. a: in belongs to TYPE A b: out belongs to TYPE B b<= a ERROR because a and b is belonging to different types Q: Why vhdl does not allow this? A: This is a kind of protection so engineer will not do different TYpe assignment by mistake

Type Data „ VHDL is a very rigid Type Data Oriented Language Q : What is it means? A : Different type can not do any assignment e.g. a : in belongs to TYPE A b : out belongs to TYPE B b <= a; ----- ERROR because a and b is belonging to different types Q : Why VHDL does not allow this ? A : This is a kind of protection, so engineer will not do different TYPE assignment by mistake