《计算机英语》Third Party EDA Tools Interface with Altera Max+Plus

Third Party EDA Tools Interface with Altera max+Plus Danny Mok Altera HK FAE (amok@altera.com) bBRA Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 Third Party EDA Tools Interface with Altera Max+Plus II Danny Mok Altera HK FAE (dmok@altera.com)

What Altera Support ■ Altera max+Pus‖ support3 Brd Party EDa tools through EDIF EDIF is a standard file transfer format between different EDA tools Synopsys Altera Max+Plus il Cadence Mentor Graphic Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 What Altera Support ◼ Altera Max+Plus II support 3rd Party EDA tools through EDIF ◼ EDIF is a standard file transfer format between different EDA tools Altera Max+Plus II Synopsys Cadence Mentor Graphic EDIF

Is it so simple ?! ? Is it true that edif can handle all the different eda tools conversion ■ Answer is Yes and no a Yes- bascially all the eda tools can accept EDIF file and understand it a No--EDa only provide major information to the EDa tools, except the EDiF file, we also need to provide a file name as LMF"--Library Mapping File Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 Is it so simple ?!?! ◼ Is it true that EDIF can handle all the different EDA tools conversion ◼ Answer is Yes and No ◼ Yes -- bascially all the EDA tools can accept EDIF file and understand it ◼ No -- EDA only provide major information to the EDA tools, except the EDIF file, we also need to provide a file name as “LMF” -- Library Mapping File

What is LMF - Library Mapping File Two Input AND gate ■ LMF is a kind of pin to pin mapping Altera eda tool gate to gate mapping Power and Ground signal mapping AND2 ■ Pin to Pin Mapping B A->1.B->2.C->3 ■ Gate to Gate Mapping AND2→>2AND ABC EDA tools 2AND Power and ground signal Mapping Vcc->Vdd Gnd -> Dand Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 What is LMF -- Library Mapping File ◼ LMF is a kind of – pin to pin mapping – gate to gate mapping – Power and Ground signal mapping ◼ Pin to Pin Mapping – A->1, B->2, C->3 ◼ Gate to Gate Mapping – AND2 -> 2AND ◼ Power and Ground signal Mapping – Vcc -> Vdd – Gnd -> Dgnd Two Input AND gate Altera EDA tools ABC EDA tools A B C 2AND 1 2 3

Example of lMF % 1-bit full adder Altera library BEGIN FUNCTION 7482(A2, Al, B2, B1, CO) RETURNS (SUM2, SUMI, C2) FUNCTion adoldI"(GND","a,GND,6,ci") RETURNs " s","co" The other EDA Library END %2-bit full adder % BEGIN FUNCTION 7482(A2, Al, B2, B1, CO) RETURNS (SUM2, SUMI, C2) FUNCTION " ad02dl"Cal, a0,"b1",bo","ci") RETURNS ("SI" s0,"co" END bBRA Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 Example of LMF % 1-bit full adder % BEGIN FUNCTION 7482 (A2,A1,B2,B1,C0) RETURNS (SUM2,SUM1, C2) FUNCTION "ad01d1" ("GND", "a", "GND", "b", "ci") RETURNS ("", "s", "co") END % 2-bit full adder % BEGIN FUNCTION 7482 (A2,A1,B2,B1,C0) RETURNS (SUM2, SUM1, C2) FUNCTION "ad02d1" ("a1", "a0", "b1", "b0", "ci") RETURNS ("s1", "s0", "co") END Altera Library The other EDA Library

Who provides the LMF a Altera will provide LMF for EDI etlA te Seting some commonly use EDA tools Cadence VShow LMF Mapping Mesager Exemplar Mentor Graphics ynopsys Synplicity 9m: Viewlogic Synplicity ■ But some minority EDa viewlogic tools need to provide by EDA vendor create by the customer itself bBRA Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 Who provides the LMF ◼ Altera will provide LMF for some commonly use EDA tools – Cadence – Exemplar – Mentor Graphics – Synopsys – Synplicity – Viewlogic ◼ But some minority EDA tools need to provide by – EDA vendor – create by the customer itself

EXample: Synopsys interface with Altera Compile Verilog design with the HDL design wth the Design Compile Compiler. FPGA Compiler. or Design Analyzer ndard Delay Format (SDF) File and use Compile VHDL design the syn2acf utility to conert ormation to with the VHDL Compiler MAX-PLUS II format Process EDIF Input File with the MAX+PLUS Il Compiler Generate EDIF Output File(s) VHDL Output File(s), verilog utput File(s), and optional SDF Output File(s) Generate programming and other files ↓↓ Program device(s) with programming Output File(s) with Output File(s) with EDIF simulation Verilog simulation ardware and hardware and other software

Copyright © 1997 Altera Corporation 2/22/2021 Example : Synopsys interface with Altera

Design Interface Design Entry Compile verilog Synthesize and optimize Generate EDIF netlist file design with the HDL design with the Design Compile Compiler, FPGA Compiler (Optional)Generate or Design Analyzer additional Standard Delay Format (SDF) File and use Compile VHDL design the syn2acf utility to convert with the VHDL Compiler timing information to MAX+PLUs‖ format bBRA Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 Design Interface

Processing Interface Project Processing Process EDIF Input File with the MAX+PLUS ll Compiler Generate EDIF Output File(s). VHDL Output File(s), Verilog Output File(s), and optional SDF Output File(s) Generate programming and other files bBRA Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 Processing Interface

Simulation Interface Device ProgrammIng Project Simulation Program device(s) Program device(s) Simulate EDIF Simulate VHDL Simulate the verilog ith programming with programming Output File(s)with Output File(s)with Output File(s)with files and Altera files and other EDIF simulation the VHDL System Verilog simulation programming programming software Simulator(VSS)or software hardware and hardware and other software software software bBRA Copyright 1997 Altera Corporation 2/22/2021

Copyright © 1997 Altera Corporation 2/22/2021 Simulation Interface