《计算机英语》Agenda What is FPGA Express

FPGA Express RESS FPGA Alan ma Senior Corporate Applications Engineer downloadfrom:http://wwwfpga.com.cn @2000 Synops ys, Inc (FE. SynoPSys

© 2000 Synopsys, Inc. (FE.1) FPGA Express Alan Ma Senior Corporate Applications Engineer download from: http://www.fpga.com.cn

Agenda Whatis FPGA Express? Design Flow Design Analysis FPGA Scripting Tool(FST) Summary Verilog Coding Styles Tips Tricks @2000 Synops ys, Inc(FE.2) SynoPSys

© 2000 Synopsys, Inc. (FE.2) Agenda What is FPGA Express? Design Flow Design Analysis FPGA Scripting Tool (FST) Summary Verilog Coding Styles Tips & Tricks

Agenda What is FPGA Express? Design Flow Design analysis FPGA Scripting Tool(fST) Summary Verilog Coding Styles Tips tricks @2000 Synopsys, Inc(FE 3 SynoPSys

© 2000 Synopsys, Inc. (FE.3) Agenda What is FPGA Express? Design Flow Design Analysis FPGA Scripting Tool (FST) Summary Verilog Coding Styles Tips & Tricks

Introduction FPGA Express(Fe) is a powerful synthesis tool for leading FPga and pld architectures The oeM version for altera is tailored to altera architectures: Architecture-specific mapping and optimization Industry-leading quality of results(Qor) Tight integration with Quartus Support for industry-standard verilog and VhDl Easy-to-use design flows and graphical user interfaces Integrated static timing analysis with Time Tracker Vista(visual tools for analysis) including schematic viewing with tight links to Time Tracker TCL-based language for scripting @2000 Synops ys, Inc(FE. 4) SynoPSys

© 2000 Synopsys, Inc. (FE.4) FPGA Express (FE) is a powerful synthesis tool for leading FPGA and PLD architectures The OEM version for Altera is tailored to Altera architectures: Architecture-specific mapping and optimization Industry-leading quality of results (QoR) Tight integration with Quartus Support for industry-standard Verilog and VHDL Easy-to-use design flows and graphical user interfaces Integrated static timing analysis with TimeTracker Vista (visual tools for analysis) including schematic viewing with tight links to TimeTracker TCL-based language for scripting Introduction

State of the Art Synthesis Architecture Specific Mapping ATOMS (O, LCELL), Carry Chains, Cascade Chains Register duplication Supports Mega Wizard Components: LPMS, CAMS, LVDSS, PLLS LPM Inference Arithmetic lpms are inferred for max devices Multiplier LPMs are inferred for ACex, APEX, and flex devices Other arithmetic operators are implemented using atoms Automatic Global Signal Mapping Glo bal Clocks Glo bal resets @2000 Synops ys, Inc(FE.5) SynoPSys

© 2000 Synopsys, Inc. (FE.5) Architecture Specific Mapping ATOMs (IO, LCELL), Carry Chains, Cascade Chains Register Duplication Supports MegaWizard Components: LPMs, CAMs, LVDSs, PLLs LPM Inference Arithmetic LPMs are inferred for MAX devices Multiplier LPMs are inferred for ACEX, APEX, and FLEX devices Other arithmetic operators are implemented using ATOMs Automatic Global Signal Mapping Global Clocks, Global Resets State of the Art Synthesis

OEM Partnership Synopsys provides Cd image and synthesis expertise CD image (with Altera licensing DLL) is provided to Altera Synopsys r&d and cae are working closely with Altera engineers Altera provides Cds, licenses and first-line technicalsupport CDs and licenses are provided to quartus and maX+plus II customers Technical support in US: sos(altera. com http://www.altera.com 1800-800-EPLD Technical Support in Japan japan@altera.com http://www.altera.com/japan 045-939-6113(Aima)or045-4772008( Patek) @2000 Synops ys, Inc(FE.6) SynoPSys

© 2000 Synopsys, Inc. (FE.6) Synopsys provides CD image and synthesis expertise CD image (with Altera licensing DLL) is provided to Altera Synopsys R&D and CAE are working closely with Altera engineers Altera provides CDs, licenses and first-line technical support CDs and licenses are provided to Quartus and MAX+plus II customers Technical Support in US: sos@altera.com http://www.altera.com 1-800-800-EPLD Technical Support in Japan: japan@altera.com http://www.altera.com/japan 045-939-6113 (Altima) or 045-477-2008 (Paltek) OEM Partnership

Altera advantage FPGA Express FPGA Compiler lI Altera edition DesignWare DC Architecture-Specific Optimization Shell Industry-Leading QoR FPGA Integration with Quartus/MAX+plus I Industry-Standard HDLs Express Push-Button Flow Built-In Static Timing Analyzer db Schematic viewer TCL-Based Scripting Language Retiming @2000 Synopsys, Inc ( FE.7) SynoPSys

© 2000 Synopsys, Inc. (FE.7) FPGA Compiler II Altera Edition FPGA Express Altera Advantage FPGA Express DC Shell .db • Architecture-Specific Optimization • Industry-Leading QoR • Integration with Quartus/MAX+plus II • Industry-Standard HDLs • Push-Button Flow • Built-In Static Timing Analyzer • Schematic Viewer • TCL-Based Scripting Language Retiming DesignWare

Agenda Whatis FPGA Express? Design Flow Design analysis FPGA Scripting Tool(FST Summary Verilog Coding styles Tips Tricks @2000 Synops ys, Inc(FE.8) SynoPSys

© 2000 Synopsys, Inc. (FE.8) Agenda What is FPGA Express? Design Flow Design Analysis FPGA Scripting Tool (FST) Summary Verilog Coding Styles Tips & Tricks

Design flow Start> Programs> Synopsys> FPGA Express to launch fe Push-Button Mode for Quick Results Easy to use Fast turn-around Create Project, Analyze, Create Implementation Optimize, Place-and-Route in Quartus (Export Netlist and then place-and-Route in MAX+plus D) Constraint Mode for Maximum Performance More control on synthesis and place-and-route results Create Project, Analyze, Create Implementation, Enter Constraints, Optimize Place-and-Route in Quartus (Export Netlist and then Place-and-Route in MAX+plusⅢ @2000 Synops ys, Inc(FE.9) SynoPSys

© 2000 Synopsys, Inc. (FE.9) Start > Programs > Synopsys > FPGA Express to launch FE Push-Button Mode for Quick Results Easy to use Fast turn-around Create Project, Analyze, Create Implementation & Optimize, Place-and-Route in Quartus (Export Netlist and then Place-and-Route in MAX+plus II) Constraint Mode for Maximum Performance More control on synthesis and place-and-route results Create Project, Analyze, Create Implementation, Enter Constraints, Optimize, Place-and-Route in Quartus (Export Netlist and then Place-and-Route in MAX+plus II) Design Flow

Push-Button mode Tool Bar represents design flow from left to right Tip Bar provides help on the next logical step Design sources window shows all design files Chips window lists the implementations s Eile Edit Synthesis Script Filters View window Help 口回田品m :妇 demo +-不 micro (Altera APE×20 KAUTOFASTEST〕 白- e wORK +.k micro-Optimized (Altera-APEX20K: AUTOFASTEST) 中- b tim hier. vhd 由- n counter4.whd B)-BY micro vhd -by convsegs. hd KKDDINErrors A Warnings A Messages For Help, press F1 @2000 Synops ys, Inc(FE.10) SynoPSys

© 2000 Synopsys, Inc. (FE.10) Tool Bar represents design flow from left to right Tip Bar provides help on the next logical step Design Sources Window shows all design files Chips Window lists the implementations Push-Button Mode