《计算机英语》Analyzing Designs Using Model Technology's Mode Sim

Analyzing Designs Using Model Technology's Modelsim
1 Analyzing Designs Using Model Technology’s ModelSim

Typical PLD Design Flow
2 Typical PLD Design Flow

Typical PLD Flow Design Specification Design Modification Design Entry RTL SImulation Design Synthesis Place route Gate Level Simulation Timing Analysis In-System Verification System Production
3 System Production Design Specification Typical PLD Flow Design Entry RTL Simulation Design Synthesis Gate Level Simulation Place & Route Timing Analysis In-System Verification Design Modification

Typical PLD Design Flow ■ Design Entry Behavioral or structural description of design RTL Simulation(ModelSim) Functional simulation Verify logic model(no timing delays used) May require design edits Synthesis Translate design into target technology primitives Optimization Meet required area and performance constraints ■Pace& Route Map the design to specific locations inside target technology Specify which routing resources should be used
4 Typical PLD Design Flow ◼ Design Entry – Behavioral or structural description of design ◼ RTL Simulation (ModelSim) – Functional simulation – Verify logic model (no timing delays used) – May require design edits ◼ Synthesis – Translate design into target technology primitives – Optimization • Meet required area and performance constraints ◼ Place & Route – Map the design to specific locations inside target technology – Specify which routing resources should be used

Typical PLD Design Flow a Gate Level Simulation(ModelSim) Timing simulation Verify design will work in target technology once programmed/configured May require design edits ■ Timing analysis a Verify performance specifications were met May require design edits ■ Board design Simulate board design Program and test device on board
5 Typical PLD Design Flow ◼ Gate Level Simulation (ModelSim) – Timing simulation – Verify design will work in target technology once programmed/configured – May require design edits ◼ Timing Analysis ◼ Verify performance specifications were met – May require design edits ◼ Board Design – Simulate board design – Program and test device on board

Modelsim overview 700LF
6 ModelSim Overview

Modelsim simulation tool a Developed by Model Technology a One of Industry's Most Popular Simulators Simulates both verilog VHDL OEM Version allows for Verilog simulation 700L OR VHD Simulation lode lechnology
ModelSim Simulation Tool ◼ Developed by Model Technology ◼ One of Industry’s Most Popular Simulators ◼ Simulates both Verilog & VHDL – OEM Version allows for Verilog simulation OR VHDL simulation

Modelsim products ■ Model sim∧ HDL or ModelSim/Verilog VLOG Checklist OEM ■Mode|Sim/LNL Licenses verilog or vhdl but not at the same time ■Mode|sim/PLUs Designer can simulate mixed Verilog VHDL at once Model sim/Se Premier version All the features of plus along with additional features
8 ModelSim Products ◼ ModelSim/VHDL or ModelSim/Verilog – OEM ◼ ModelSim/LNL – Licenses Verilog or VHDL but not at the same time ◼ ModelSim/PLUS – Designer can simulate mixed Verilog & VHDL at once ◼ ModelSim/SE – Premier version – All the features of PLUS along with additional features

Modelsim OEM Features a Complete Standards Support 87 VHDL 93 VHDL IEEE 1364-95 Verilog SDF1.0-3.0 ViTAL 2.2b VITAL 95 Easy-to-use Interface Common across platforms
9 ModelSim OEM Features ◼ Complete Standards Support – ‘87 VHDL – ‘93 VHDL – IEEE 1364-’95 Verilog – SDF 1.0 - 3.0 – VITAL 2.2b – VITAL ‘95 ◼ Easy-to-use Interface – Common across platforms

Simulation with Modelsim Model Technology
10 Simulation with ModelSim
按次数下载不扣除下载券;
注册用户24小时内重复下载只扣除一次;
顺序:VIP每日次数-->可用次数-->下载券;
- 《计算机英语》How to use LPM within VHDL Entry.ppt
- 《计算机英语》Agenda What is FPGA Express.ppt
- 《计算机英语》Usage of FloorPlanner.ppt
- 《计算机英语》Third Party EDA Tools Interface with Altera Max+Plus.ppt
- 《计算机英语》How to implement the circuit in EAB within VHDL coding.ppt
- 《计算机英语》Mix Design Entry within Max+Plus ll.ppt
- 《计算机英语》Compilation is too Long.ppt
- 《计算机英语》Design of Combinational Circuit.ppt
- 《计算机英语》Powerful of CLIQUE.ppt
- 《计算机英语》Asynchronous Circuit Design.ppt
- 《计算机英语》AHDL Training class.ppt
- 《大学英语》课程教学资源(六级考试历年全真试卷)Model test one Part I Listening Comprehension(20 minutes).doc
- 《大学英语》课程教学资源(六级考试历年全真试卷)Model Test One Part I Section A答案部分.doc
- 《大学英语》课程教学资源(六级考试历年全真试卷)Part two试卷部分.doc
- 《大学英语》课程教学资源(六级考试历年全真试卷)Part Three答案部分.doc
- 《新视野大学英语》课程教学资源(备课笔记)book2 Unit 9.doc
- 《新视野大学英语》课程教学资源(备课笔记)book2 Unit 8.doc
- 《新视野大学英语》课程教学资源(备课笔记)book2 Unit 6.doc
- 《新视野大学英语》课程教学资源(备课笔记)book2 Unit4.doc
- 《新视野大学英语》课程教学资源(备课笔记)book2 Unit3.doc
- 《计算机英语》MPII Quickstart Chinese.ppt
- 《计算机英语》Multiple clock System Design.ppt
- 《计算机英语》Setup/Hold Time Problem.ppt
- 《计算机英语》Design Requirement.ppt
- 《计算机英语》Tri-State Buffer.ppt
- 《计算机英语》Beginner VHDL Training Class.ppt
- 西北大学:《综合英语》Test for New Integrated English Band i (1-A).doc
- 西北大学:《综合英语》Oral Test for New Integrated English Band(1-A).doc
- 西北大学:《综合英语》Test for New Integrated English Band I(1-A).doc
- 西北大学:《综合英语》Oral Test for New integrated english Band I(1-B).doc
- 西北大学:《综合英语》Oral Test for New Integrated English Band(2-B).doc
- 西北大学:《综合英语》Test on New Integrated English Test A(Band II, June, 2004).doc
- 西北大学:《综合英语》Key to the Test a (Band Il, June, 2004).doc
- 西北大学:《综合英语》Test for New Integrated English(11).doc
- 西北大学:《综合英语》Test for New Integrated English Band I (1-B).doc
- 西北大学:《综合英语》Test for New Integrated English Band I (1-B).doc
- 西北大学:《综合英语》Key to The Test for New Integrated English(II).doc
- 西北大学:《综合英语》Oral Test for New Integrated English Band II (2-A).doc
- 西北大学:《综合英语》Unit 1 College Life.ppt
- 西北大学:《综合英语》Unit 2 Perseverance.ppt