电子科技大学：《电子设计自动化技术》课程教学资源（讲义课件）补充内容

esTc 设计中 电子设计自动化技术 教师:李平教授(博导) Email: pliQuestc. edu.cn Te:83201794

设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794

esTc 设计中 电子设计自动化技术 补充内容 Model Referencing of Library/Package Implied Process and Explicit Process Combinatorial Process and Sequential Process

设计中心 电子设计自动化技术 补充内容 Model Referencing of Library/Package Implied Process and Explicit Process Combinatorial Process and Sequential Process

esTc 设计中 VHDL VHSIC( Very High Speed Integrated Circuit Hardware Description Language

设计中心 VHDL • VHSIC (Very High Speed Integrated Circuit) • Hardware • Description • Language

VHDL描述的总体结构 Package Generics Entity Architecture Architecture Architecture (Data Flow) (Behavioral) (structural) oncurrentConcurrent Process tatements Statements Sequential Statements

VHDL设计中心 描述的总体结构

esTc 设计中 Behavior Modeling Only the functionality of the circuit, no structure No specific hardware intent For the purpose of synthesis, as well as simulation N1,,,|Nn F in1 THEN ①UT1,,OUTn FOR j IN high DOWNTO low LOOP shft(): =shft() END LOOP out1 < shft AFTER 5ns

设计中心 Behavior Modeling • Only the functionality of the circuit, no structure • No specific hardware intent • For the purpose of synthesis, as well as simulation IN1，…，INn IF in1 THEN OUT1，…，OUTn FOR j IN high DOWNTO low LOOP shft(j) := shft(j); END LOOP; out1 <= shft AFTER 5ns

esTc 设计中 Structural Modeling e Functionality and structure of the circuit Call out the specific hardware For the purpose of synthesis Higher-level Component INT OUT1 Lower-level Component2 INn Lower-level Component 1 oUTn

设计中心 Structural Modeling • Functionality and structure of the circuit • Call out the specific hardware • For the purpose of synthesis Lower-level Component1 Lower-level Component2 IN1 INn OUT1 OUTn Higher-level Component

RTL SYnthesis Process(a, b, c, d, sel) begin inferred abcd mux out case(sel)is When 00"=>mux out mux out mux out mux out<=d end case Translation Optimization

esTc 设计中 Model Referencing of Library/Package

设计中心 Model Referencing of Library/Package

esTc 设计中 VHDL Operators Operator Type Operator Name/Symbol Logical and or nand nor xor xnor(93 E Relational > Adding -8 Signing Multiplying x mod rem Miscellaneous abs not

设计中心 VHDL Operators Operator Type Operator Name/Symbol Logical and or nand nor xor xnor(93) Relational = /= >= Adding + - & Signing + - Multiplying * / mod rem Miscellaneous ** abs not

esTc 设计中 VHDL Operators Vhdl defines arithmetic boolean functions only for built-in data types ( defined in Standard package) Arithmetic operators such as +, 5 are defined only for INTEGER type Boolean operators such as AND, OR, NOt are defined only for BIT type

设计中心 VHDL Operators • VHDL defines Arithmetic & Boolean functions only for built-in data types (defined in Standard package) – Arithmetic operators such as +, -, , = are defined only for INTEGER type. – Boolean operators such as AND, OR, NOT are defined only for BIT type