《微机技术与仪器系统设计》课程教学资源（芯片手册）Intel 8253 三通道计数器芯片

intel. 8253/8253-5 PROGRAMMABLE INTERVAL TIMER MCS-85TM Compatible 8253-5 3 Independent 16-Bit Counters ■DCto2.6MH ■Available in EXPRESS Programmable Counter Modes Extended Tempraturnge I9hces5868Ma8eyT2aongef5epgenegpcge24pmpseOmperpepher &pe98g2838g8sr9smS1counles6aohwnha6eounaieodpo26M收Aumoeeod -GATEO CLK 1 ATE OUT 8253 GATE GNO 12 13DOUT -OUT 2 231306-2 NTERNAL BUS 231306- Figure 1.Block Diagram 3-51 rder m

intel 8253/8253-5 FUNCTIONAL DESCRIPTION RD(Read) A"low"on this input informs the 8253 that the CPU General is inputting data in the form of a counters value. w丽(Write) form of loading counters The 8253 solves one of the most common proble A0,A1 These inputs are normally connected to the address one of the counters of the 8253 bus. The r function is to select one of the three coun desired q anity.then upon tor mode selection. aooress the contr ent ot CS(Chip Select) priority levels. A "low"on this input enables the 8253.No reading Other counter/timer functions that are non-delay in the device s selecte tion of the counters. Programmable Rate Generator 。Event Counter .Binary Rate Multiplier ·Real Time Clock -GATE ·Digital One-Sho .Complex Motor Controller Data Bus Buffer tions.The Data Bus MODES of the 8253 3.Reading the count values. Read/Write Logic The Read/Write Logic accepts inputs from the sys. INTERNALUS ous and in turn 231306-3 tem edordisabled by 298a8oem2o8h8 Figure 3.Bl ck Diagram ving Data Bus /Write Logic F ction 3-52

intel 8253/8253-5 CSDW丽A1A0 010 oo Load Counter No o register for MODE programming. 0 1 001 Load Counter No.1 0 Load Counter No.2 Basically.the select inputs A0.A1 connect to the Write Mode Word 0o 10I 0 Read Counter No.0 ear select method.Or it can be conr 00 10 1 Read Counter No 1 0 0 11 0 Read Counter No 2 Sy%RoAngtadocode,sUchasaninai92o5orlarg8 0011 No-Operation 3-State x Disable 3-State 11 xX No-Operation 3-State Control Word Register A0.A soesrcoaregsterTheainto TE ction of binary or BCD counting OUT 1 33 o rea s contents is available CLK Z GATE Counter #0,Counter #1,Counter #2 nsists of a single.16-bit,pre-settable can outp 231306-4 Block Diagram Showing Control Word Hegister anc eration,binary or BCD.AIS o.there are special te ADDRESS AUS1 thees in th contr vare overne can be minimized for these functions. ds and lo can be read"on 8253 SYSTEM INTERFACE Rmgeomggnera6 The 231306-5 Figure 5.8253 System Interface 3.53

intel 8253/8253-5 OPERATIONAL DESCRIPTION RL-READ/LOAD: RL1 RLO General 0 I Counter Latching operation (see READ/WRITE Procedure Section). The complete functional definition of the 8253 10 Read/Load most significant byte only 01 each counter Read/Load least significant byte only. MODE 1 1 then most si ficant byte first, vte d.The se control words program the M M-MODE M2 M1 MO 0 0 Mode 0 ual counting 0 0 Mode 1 ona logic is pro on-chip som g and mproblems 0 Mode 2 ent of exte Mode3 o the microcom 0 0 Mode 4 0 Mode5 Programming the 8253 BCD: Binary Counter 16-Bits Binary Coded Decimal(BCD)Counter (4 Decades Counter Loading Control Word Format The D7 D6 D5 D4 D3 D2 D1 Do selected by the RL SC1 SCO RL1 RLO M2M1 MO BCD its).follow ed by a rising edge rior to that aling may yield invalid data. Definition Of Control MODE DEFINITION SC-SELECT COUNTER: MODE 0:Interrupt on Terminal Count.The outpu SC1 sco will be in after th mode set oper 0 0 Select Counter o 0 Select Counter 1 en terminal count is reac hed.theo 0 Select Counter 2 edwith the mode or a new count is load The eaaandecrementaherterl 3-54

intel. 8253/8253-5 In Modes 2 and 3.if a CLK source other than the gate input. e.After the the succeeding trig the gate input. unt after any rising edge of count will be inhibited while the GATE input is low. MODE 5:Hardware Trigs red Strobe.The counter nting after the rising edge of the trigge the next eq rminal count is reached.The counter is retn the count register is reloaded betwe not go low until the full count Signal Status Or Goino Rising High 3 Modes Low Thus.the gate input can be 0 Disables counting 1 1)Initiates then can aiso be synchronized by software counting 2) sets outpu one ha count been con 1)Disables 1)Reloads Enables This isa om ished by decrementing the 2)Set ounte counting k pulse.Whe nged and the counter high nt and the whole process is repeated. 3 1)Disables 1)Reloads Enables if the count is odd and the output is high,the firs 2)Sets unt by 1.Su uent clock uls imm high the ck by 2. the output goes lov 4 Disab Enables counting lock pu decrement the count b Initiates this way.if the count is odd,the ou put will be hia counting or (N 1)/2 counts and low for (N-1)/2 counts Flgure 6.Gate Pin Opera ations 3-55

intel. 8253/8253-5 MODE 0:INTERRUPT ON TERMINAL COUNT MODE 3:SQUARE WAVE GENERATOR OUTPUT=角_了 231306-9 MODE 4:SOFTWARE TRIGGERED STROBE GATI- CLOCK几几几nn几nnnn几un ATPUT IINTIA南U用 n4f A+m 231306-6 OUTPUT MODE 1:PROGRAMMABLE ONE-SHOT aoKnnnnnnnnnnnnn LOAD=4厂 mn了 GATE TRIGGER OUTPUT OUTPUT 231306-10 MODE 5:HARDWARE TRIGGERED STROBE RIGGER adnnnnnnnsnnnnn OUTPUT GATE 231306-7 OUTPUT 4) MODE 2:RATE GENERATOR aocnnnnnnnnnnnnnnn GATE 231306-11 RESET 231306-8 Figure 7.8253 Timing Diagrams 3-56

intel. 8253/8253-5 8253 READ/WRITE PROCEDURE MODE Control Word Write Operations nter n LSB The syrercu Counter Register byte Counter n programmer must write out to the 8253a MODE MSB Counter Register byte Counter n counter NOTE: used Figure 8.Programming Format counter's MODE control word register has a se (0)com A1 AD No.1 MODE Control Word 1 Counter 0 No.2 MODE C Word 11 3 ance inde Counter1 en a select d count reg No.3 MODE Control Word Counter 2 11 ber of bytes p med in the MoDE (RLO.RL1).The one or two bytes to be loaded in th No.4 LSB Count Register Byte Counter 1 01 MODE contol word can be ramm ed at No.5 MSB DE control Count Register Bye 0 No.6 LSB Count Register Byte Counter 2 1 All counters No.7 MSB 10 will not restart No.8 LSB Count Register Byte for BC coun Counter 0 00 of two No.9 MSB Count Register Byte Counter 0 00 NOTE: ake use of the device Figure 9.Alternate Programming Formats 3-57

intel 8253/8253-5 Read Operations Read Operation Chart A1 A0 RD 0 Read Counter No.0 Read Counter No. 0 0 Read Counter No.2 1 o lllegal nu6amghaactacount9npre9r8s mer car Reading While Counting puts to the 8253 the program can select the ng operation the 825 3 has s tion of the mode he when the programmer only requ am8wn o.A) wishes to d the this met nod is that in order t con the cial code which latches the present count value int trol ling the Gate input o Dyex a storage register Th er then is ues a no to t the selected MODE Register for Latching Count Se ond I/O Read contains the most significant byte S A0,A1=11 Due to the internal logic of the 8253 it is absolutely D7 D6 D5 D4 D3D2D1 DO ssary to complete the sntioe sc1s000×X ng WR com 8S1b8cn-32c的caaes8lheneteng6pea ecify counter to be latched. -don't care. counter's mode. 1.SMHz CL 2 8085 82535 1306-12 an 805 clock output is to drive an 8253-5 cock inputmust be reduced to 2MHzo es Figure 10.MCS-85TM Clock Interface 3-58

intel. 8253/8253-5 ABSOLUTE MAXIMUM RATINGS NOTICE-Thi atasheet The spcf Ambient Temperature Under Bias.C to70C WARNING:Stres vice bevond the "Absolut Storage Ter ature -65Cto+150°C .-0.5Vto7N nCondionsn Power Dissipation .Wat may affect device reli D.C.CHARACTERISTICS TA -0'C to 70'C,Vcc 5V +10% Symbol Parameter Min Max Unit Test Conditions Vu Input Low Voitage -0.5 0.8 V VH .Input High Voltage 2.2 VCC +.5V V Output Low Voltage 0.45 (Note 1) VoH Output High Voltage 2.4 V (Note 2) Input Load Current ±10 VIN =Vcc to ov lOFL Output Float Leakage ±10 uA VoUT Vcc to 0.45V Vcc Supply Current 140 mA 3 CAPACITANCE TA 25*C.Vcc GND OV Symbol Parameter Min Typ Max Unit Test Conditions CIN Input Capacitance 10 pF fc=1 MHz I/O Capacitance 20 pF Unmeasured pins returned to Vss A.C.CHARACTERISTICS TA =oC to 70'C,Vcc -5.0V +10%.GND OV Bus Parameters(3) READ CYCLE 8253 8253-5 Symbol Parameter Min Max Min Unit Max tAR Address Stable before READ 50 ns tBA Address Hold Time for READ 5 5 ns READ Pulse Width 400 300 ns t8D Data Delay from Read(4) 300 200 toF READ to Data Floating 25 125 25 100 ns Recovery Time between READ 1 and Any Other Control Signal 3-59

intel 8253/8253-5 A.C.CHARACTERISTICS (Continued) WRITE CYCLE 8253 8253-5 Symbol Parameter Unit Min Max Min Max tAW Address Stable before WRiTE 5 twA Address Hold Time for WRITE 0 tww WRITE Pulse Width 400 300 ns tow Data Set Up Time for WRITE 300 250 twD Data Hold Time for WRITE 40 30 ns tRV Recovery Time between WRITE 1 1 and Any Other Control Signal CLOCK AND GATE TIMING 8253 8253-5 Symbol Parameter Min Max Min Unit Max tCLK Clock Period 380 380 tPWH High Pulse Width 230 230 ns tPWL Low Pulse Width 150 150 tGw Gate Width High 150 150 ns tGL Gate Width Low 100 100 ns Gate Set Up Time to CLKT 100 100 ns tGH Gate Hold Time after CLKT 50 50 ns top Output Delay from CLK(4) 400 400 ns Output Delay from Gate(4) 300 300 ns 0E2 2.lo tim asured at VoH 2.2.VoL -0.8. A.C.TESTING INPUT,OUTPUT WAVEFORM A.C.TESTING LOAD CIRCUIT 24 警 150p 23130t 231306-14 3-60