轨至轨运放的设计（PPT课件讲稿）RAIL-to-RAIL OP AMPS

RAIL-to-RAIL OP AMPS 轨至轨运放的设计

RAIL-to-RAIL OP AMPS 轨至轨运放的设计

主要内容 设计原理 ·采用电平移位法轨至轨运放的设计 采用恒定电压法实现跨导恒定的设计

主要内容 • 设计原理 • 采用电平移位法轨至轨运放的设计 • 采用恒定电压法实现跨导恒定的设计

Op Amp Configurations R2 RI O RI R2 R2 R2 RI I+ RI 十 RI Vo+ VI+ RI R2 R2 (d) (e)

Op Amp Configurations

Why rail-to-Rail Differential Input Stage? Configuration Figure Input common mode Output voltage voltage swing SWIng Inverting (a) Non-inverting RI/(RI+R2)" VSUP Voltage follower Rail-to-rail Fully differential (d) R2/(RI+R2)VICM FD to se e R2/(RI+R2)Vi

Why Rail-to-Rail Differential Input Stage?

问题 为什么要提高运放的输入信号共模范围? 为什么要实现跨导的恒定?

问题 • 为什么要提高运放的输入信号共模范围？ • 为什么要实现跨导的恒定？

How to obtain a rail-to-Rail Input Common Mode Range? To the next stage Vit Vit To the next stage (a P-type differential input stage (b)N-type differential input stage

How to Obtain a Rail-to-Rail Input Common Mode Range? (a) P-type differential input stage (b) N-type differential input stage

How to obtain a rail-to-Rail Input Common Mode Range? GS CMR( Common Mode ra Vdd gIm SG. M1,2 Vit MI M2 CMR Input commonl lode voltage range To the next Input common stage Mode voltage Vss Vdd Vicm Where V=v, +v T

How to Obtain a Rail-to-Rail Input Common Mode Range?

How to obtain a rail-to-Rail Input Common Mode range? 圖Va國 VGs V( Common mode range) To the next Vdd stage gm CMRI Vit Input common mdde voltage range Input Common Mode voltage Vad

How to Obtain a Rail-to-Rail Input Common Mode Range?

combining a PMOS and a NMos Differential pairs Mb3 V M4 dsat CMR Vdd There is an overlap between VcMRP and c CMR N Thus the minImum power supply voltage MI M3 M4/M2 requirement yields > (4Vdsat+VTN+VTP Mb2 Mb1 P Pair N Pair

combining a PMOS and a NMOS Differential pairs

combining a PMOS and a NMos Differential pairs gm gm. the sum of RegionⅡ/ gmN and gmp Region i Region Ii lp AID gIm Vdd Common Mode voltage

combining a PMOS and a NMOS Differential pairs